MT28C3212P2NFL-11TET datasheet, PDF

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MT28C3212P2NFL-11TET: DescriptionMemory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA66, FBGA-66; Categorystorage storage; File Size815KB，47 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT28C3212P2NFL-11TET Overview

Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA66, FBGA-66

MT28C3212P2NFL-11TET Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	BGA
package instruction	FBGA-66
Contacts	66
Reach Compliance Code	unknown
Maximum access time	110 ns
Other features	SRAM ORGANISATION IS 128K X 16
JESD-30 code	R-PBGA-B66
JESD-609 code	e0
length	12 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Number of functions	1
Number of terminals	66
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA66,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	1.8/2 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.00006 A
Maximum slew rate	0.025 mA
Maximum supply voltage (Vsup)	2.2 V
Minimum supply voltage (Vsup)	1.65 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm

MT28C3212P2NFL-11TET Preview

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

FLASH AND SRAM

COMBO MEMORY

FEATURES

• Flexible dual-bank architecture

• Support for true concurrent operations with no

latency:

Read bank

during program bank

and vice versa

Read bank

during erase bank

and vice versa

• Organization: 2,048K x 16 (Flash)

128K x 16 (SRAM)

• Basic configuration:

Flash

Bank

(4Mb Flash for data storage)

– Eight 4K-word parameter blocks

– Seven 32K-word blocks

Bank

(28Mb Flash for program storage)

– Fifty-six 32K-word main blocks

SRAM

2Mb SRAM for data storage

– 128K-words

• F_V

, V

Q, F_V

, S_V

voltages

1.65V (MIN)/1.95V (MAX) F_V

read voltage or

1.80V (MIN)/2.20V (MAX) F_V

read voltage

1.65V (MIN)/1.95V (MAX) S_V

read voltage or

1.80V (MIN)/2.20V (MAX) S_V

read voltage

1.65V (MIN)/1.95V (MAX) V

Q or

1.80V (MIN)/2.20V (MAX) V

1.80V (TYP) F_V

(in-system PROGRAM/ERASE)

0.0V (MIN)/2.20V (MAX) F_V

(in-system

PROGRAM/ERASE)

12V ±5% (HV) F_V

(production programming

compatibility)

• Asynchronous access time

Flash access time: 100ns or 110ns @ 1.65V F_V

SRAM access time: 100ns @ 1.65V S_V

• Page Mode read access

Interpage read access: 100ns/110ns @ 1.65V F_V

Intrapage read access: 35ns/45ns @ 1.65V F_V

• Low power consumption

• Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank

PROGRAM-SUSPEND-to-READ within same bank

ERASE-SUSPEND-to-PROGRAM within same bank

• Read/Write SRAM during program/erase of Flash

• Dual 64-bit chip protection registers for security

purposes

• PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

MT28C3212P2FL

MT28C3212P2NFL

Low Voltage, Extended Temperature

BALL ASSIGNMENT

66-Ball FBGA (Top View)

A20

A11

A15

A14

A13

A12

F_V

A16

A10

DQ15

S_WE#

DQ14

DQ7

F_WE#

DQ13

DQ6

DQ4

DQ5

S_V

F_RP#

DQ12

S_CE2

S_V

F_V

F_WP#

F_V

A19

DQ11

DQ10

DQ2

DQ3

S_LB#

S_UB#

S_OE#

DQ9

DQ8

DQ0

DQ1

A18

A17

S_CE1#

F_V

F_CE#

F_V

F_OE#

Top View

(Ball Down)

• Cross-compatible command set support

Extended command set

Common Flash interface (CFI) compliant

NOTE:

1. These specifications are guaranteed for operation

within either one of two voltage ranges, 1.65V–1.95V

or 1.80V–2.20V. Use only one of the two voltage

ranges for PROGRAM and ERASE operations.

2. MT28C3212P2NFL only.

OPTIONS

MARKING

• Timing

100ns

-10

110ns

-11

• Boot Block

Top

Bottom

• V

Range

0.9V–2.2V

None

0.0V–2.2V

• Operating Temperature Range

Commercial Temperature (0

C to +70

C) None

Extended Temperature (-40

C to +85

C) ET

• Package

66-ball FBGA (8 x 8 grid)

Part Number Example:

MT28C3212P2FL-10 TET

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

GENERAL DESCRIPTION

The MT28C3212P2FL and MT28C3212P2NFL com-

bination Flash and SRAM memory devices provide a

compact, low-power solution for systems where PCB

real estate is at a premium. The dual-bank Flash is a

high-performance, high-density, nonvolatile memory

device with a revolutionary architecture that can sig-

nificantly improve system performance.

This new architecture features:

• A two-memory-bank configuration supporting

dual-bank burst operation;

• A high-performance bus interface providing a fast

page data transfer; and

• A conventional asynchronous bus interface.

The device also provides soft protection for blocks

by configuring soft protection registers with dedicated

command sequences. For security purposes, dual 64-

bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). The WSM simplifies these operations

and relieves the system processor of secondary tasks.

An on-chip status register, one for each bank, can be

used to monitor the WSM status to determine the

progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-

ware packages.

The device takes advantage of a dedicated power

source for the Flash device (F_V

) and a dedicated

power source for the SRAM device (S_V

), both at

1.65V–1.95V or 1.80V–2.20V for optimized power con-

sumption and improved noise immunity. The

MT28C3212P2FL and MT28C3212P2NFL devices sup-

port two V

voltage ranges, V

and V

. V

is an in-

circuit voltage of 0.9V–2.2V (MT28C3212P2FL) or 0.0V–

2.2V (MT28C3212P2NFL). V

is the production com-

patibility voltage of 12V ±5%. The 12V ±5% V

is sup-

ported for a maximum of 100 cycles and 10 cumulative

hours. See Table 1.

The MT28C3212P2FL and MT28C3212P2NFL de-

vices contain an asynchronous 2Mb SRAM organized

as 128K-words by 16 bits. These devices are fabricated

using an advanced CMOS process and high-speed/

ultra-low-power circuit technology.

The MT28C3212P2FL and MT28C3212P2NFL de-

vices are packaged in a 66-ball FBGA package with

0.80mm pitch.

DEVICE MARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 2.

Table 1

Voltage Ranges

DEVICE

MT28C3212P2FL

MT28C3212P2NFL

VOLTAGE RANGE

0.9V–2.2V 11.4V–12.6V

0.0V–2.2V 11.4V–12.6V

Table 2

Cross Reference for Abbreviated Device Marks

PART NUMBER

MT28C3212P2FL-10 BET

MT28C3212P2FL-10 TET

MT28C3212P2FL-11 BET

MT28C3212P2FL-11 TET

MT28C3212P2NFL-11 TET

PRODUCT

MARKING

FW443

FW442

FW444

FW433

FW445

SAMPLE

MARKING

FX443

FX442

FX444

FX433

FX445

MECHANICAL

SAMPLE MARKING

FY443

FY442

FY444

FY433

FY445

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

PART NUMBERING INFORMATION

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Valid combinations of features and their correspond-

ing part numbers are listed in Table 3.

Figure 1

Part Number Chart

MT 28C 321 2 P 2 N FL-11 T ET

Micron Technology

Flash Family

28C = Dual-Supply Flash/SRAM Combo

Operating Temperature Range

None = Commercial (0ºC to +70ºC)

ET = Extended (-40ºC to +85ºC)

Boot Block Starting Address

B = Bottom boot

T = Top boot

Density/Organization/Banks

321 = 32Mb (2,048K x 16)

bank

= 1/8; bank

= 7/8

Access Time

-10 = 100ns

-11 = 110ns

SRAM Density

2 = 2Mb SRAM (128K x 16)

Package Code

Read Mode Operation

P = Asynchronous/Page Read

FL = 66-ball FBGA (8 x 8 grid)

PP1

Range

Operating Voltage Range

2 = 1.65V–1.95V or 1.80V–2.20V

None = 0.9V–2.2V

N = 0.0V–2.2V

Table 3

Valid Part Number Combinations

RANGE

0.9V–2.2V

0.0V–2.2V

ACCESS

TIME (ns)

100

110

BOOT BLOCK

STARTING

ADDRESS

Bottom

Top

Bottom

Top

OPERATING

TEMPERATURE

RANGE

-40

C to +85

-40

C to +85

-40

C to +85

-40

C to +85

-40

C to +85

PART NUMBER

MT28C3212P2FL-10 BET

MT28C3212P2FL-10 TET

MT28C3212P2FL-11 BET

MT28C3212P2FL-11 TET

MT28C3212P2NFL-11 TET

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

BLOCK DIAGRAM

F_WE#

F_OE#

F_CE#

F_RP#

A17

–

A20

F_V

FLASH

F_V

Bank

F_WP#

F_V

2,048K x 16

Bank

DQ0

–

DQ15

SRAM

128K x 16

S_V

–

A16

S_CE1#

S_CE2

S_OE#

S_WE#

S_V

S_UB#

S_LB#

FLASH FUNCTIONAL BLOCK DIAGRAM

PR Lock

Query

Query/OTP

OTP

DQ0-DQ15

X DEC

Data Input

Buffer

Data

F_RST#

F_CE#

F_WE#

F_OE#

Program/

Erase

Pump Voltage

Generators

Output

Multiplexer

DQ0–DQ15

Y/Z DEC

Bank 1 Blocks

Y/Z Gating/Sensing

Manufacturer’s ID

Device ID

Block Lock

RCR

ID Reg.

CSM

Status

Reg.

WSM

I/O Logic

Output

Buffer

A0–A20

Address

Input

Buffer

Address

CNT/WSM

Address

Multiplexer

Y/Z DEC

X DEC

Y/Z Gating/Sensing

Bank 2 Blocks

Address Latch

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

BALL DESCRIPTIONS

66-BALL FBGA

NUMBERS

A3, A4, A5, A6,

A7, A8, B3, B4,

B5, B6, E5, G3,

G4, G5, G6, G7,

G8, G9, H4, H5,

SYMBOL

A0–A20

TYPE

Input

DESCRIPTION

Address Inputs: Inputs for the addresses during READ and WRITE

operations. Addresses are internally latched during READ and WRITE

cycles. Flash: A0–A20; SRAM: A0–A16.

F_CE#

F_OE#

F_WE#

F_RP#

Input

Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,

the device is disabled and goes into standby power mode.

Flash Output Enable: Enables Flash output buffers when LOW. When

F_OE# is HIGH, the output buffers are disabled.

Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.

F_WE# is active LOW.

Reset. When F_RP# is a logic LOW, the device is in reset, which drives

the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,

the device is in standard operation. When F_RP# transitions from logic

LOW to logic HIGH, the device resets all blocks to locked and defaults to

the read array mode.

Flash Write Protect. Controls the lock down function of the flexible

locking feature.

SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level

deselects the SRAM and reduces the power consumption to standby

levels.

SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level

deselects the SRAM and reduces the power consumption to standby

levels.

SRAM Output Enable: Enables SRAM output buffers when LOW. When

S_OE# is HIGH, the output buffers are disabled.

SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.

S_WE# is active LOW.

SRAM Lower Byte: When LOW, it selects the SRAM address lower byte

(DQ0–DQ7).

SRAM Upper Byte: When LOW, it selects the SRAM address upper byte

(DQ8–DQ15).

Data Inputs/Outputs: Input array data on the second CE# and WE#

cycle during PROGRAM command. Input commands to the command

user interface when CE# and WE# are active. Output data when CE#

and OE# are active.

G10

F_WP#

S_CE1#

Input

S_CE2

Input

S_OE#

S_WE#

S_LB#

S_UB#

Input

B7, B9, B10, DQ0–DQ15

Input/

C7, C8, C9,

Output

C10, D7, E6,

E8, E9, E10,

F7, F8, F9, F10

(continued on next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

MT28C3212P2NFL-11TET Related Products

	MT28C3212P2NFL-11TET	MT28C3212P2FL-11BET	MT28C3212P2FL-11TET
Description	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA66, FBGA-66	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA66, FBGA-66	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA66, FBGA-66
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	BGA	BGA	BGA
package instruction	FBGA-66	FBGA-66	FBGA-66
Contacts	66	66	66
Reach Compliance Code	unknown	not_compliant	not_compliant
Maximum access time	110 ns	110 ns	110 ns
Other features	SRAM ORGANISATION IS 128K X 16	SRAM ORGANISATION IS 128K X 16	SRAM ORGANISATION IS 128K X 16
JESD-30 code	R-PBGA-B66	R-PBGA-B66	R-PBGA-B66
JESD-609 code	e0	e0	e0
length	12 mm	12 mm	12 mm
memory density	33554432 bit	33554432 bit	33554432 bit
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16	16
Mixed memory types	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM
Number of functions	1	1	1
Number of terminals	66	66	66
word count	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	2MX16	2MX16	2MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA
Encapsulate equivalent code	BGA66,8X12,32	BGA66,8X12,32	BGA66,8X12,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	1.8/2 V	1.8/2 V	1.8/2 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm
Maximum standby current	0.00006 A	0.00006 A	0.00006 A
Maximum slew rate	0.025 mA	0.025 mA	0.025 mA
Maximum supply voltage (Vsup)	2.2 V	2.2 V	2.2 V
Minimum supply voltage (Vsup)	1.65 V	1.65 V	1.65 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm

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