M54HC280D datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> M54HC280D

M54HC280D: DescriptionHC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14; Categorylogic logic; File Size210KB，9 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

Download Datasheet Parametric Compare View All

M54HC280D Overview

HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14

M54HC280D Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	not_compliant
series	HC/UH
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
length	19 mm
Logic integrated circuit type	PARITY GENERATOR/CHECKER
Number of digits	9
Number of functions	1
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/6 V
propagation delay (tpd)	290 ns
Certification status	Not Qualified
Filter level	ESCC9000
Maximum seat height	3.7 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

Preview

Download Datasheet

View All

M54HC280

RAD-HARD 9 BIT PARITY GENERATOR

HIGH SPEED:

= 22ns (TYP.) at V

= 6V

LOW POWER DISSIPATION:

=4µA(MAX.) at T

=25°C

HIGH NOISE IMMUNITY:

NIH

= V

NIL

= 28% V

(MIN.)

SYMMETRICAL OUTPUT IMPEDANCE:

| = I

= 4mA (MIN)

BALANCED PROPAGATION DELAYS:

PLH

≅

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 280

SPACE GRADE-1: ESA SCC QUALIFIED

50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

DEVICE FULLY COMPLIANT WITH

SCC-9208-003

DILC-14

FPC-14

ORDER CODES

PACKAGE

DILC

FPC

M54HC280D

M54HC280K

DESCRIPTION

The M54HC280 is an high speed CMOS 9-BIT

PARITY GENERATOR fabricated with silicon gate

MOS technology.

PIN CONNECTION

-O

It is composed of nine data inputs (A to I) and odd/

even parity outputs (ΣODD and

ΣEVEN).

The nine

data inputs control the output conditions. When

the number of high level input is odd,

ΣODD

output is kept high and

ΣEVEN

output low.

Conversely, when the output is even,

ΣEVEN

output is kept high and

ΣODD

low.

The IC generates either odd or even parity making

it flexible application. The word-length capability is

easily expanded by cascading.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC280D1

M54HC280K1

April 2004

1/9

M54HC280D Related Products

	M54HC280D	M54HC280K1	M54HC280D1
Description	HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14	HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14	HC/UH SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14
Is it lead-free?	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	DIP	DFP	DIP
package instruction	DIP, DIP14,.3	DFP, FL14,.3	DIP, DIP14,.3
Contacts	14	14	14
Reach Compliance Code	not_compliant	not_compliant	not_compliant
series	HC/UH	HC/UH	HC/UH
JESD-30 code	R-CDIP-T14	R-CDFP-F14	R-CDIP-T14
JESD-609 code	e0	e0	e0
length	19 mm	9.95 mm	19 mm
Logic integrated circuit type	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
Number of digits	9	9	9
Number of functions	1	1	1
Number of terminals	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP	DIP
Encapsulate equivalent code	DIP14,.3	FL14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2/6 V	2/6 V	2/6 V
propagation delay (tpd)	290 ns	290 ns	290 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	6 V	6 V	6 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V
Nominal supply voltage (Vsup)	4.5 V	4.5 V	4.5 V
surface mount	NO	YES	NO
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	FLAT	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	6.91 mm	7.62 mm
Maximum seat height	3.7 mm	-	3.7 mm

Recommended Resources

Homemade motorcycle anti-theft alarm horn circuit diagram

Power outage alarm circuit

Adjustable crossover point balanced subwoofer circuit

C618K-1 type ordinary lathe electrical wiring control circuit

Light controlled anti-theft alarm circuit

One of the positive and negative output voltage integrated regulated power supply circuits

Introduction to TI_DSP link command file (*.cmd): A complete DSP program consists of at least three parts: program code, interrupt vector table, and link command file (or link configuration file) (*.cmd).The link configuration file determines the opt...; Aguilera Microcontroller MCU

TI CC1310 sub1G SDK development unique identification number MAC address reading: easyLink API, 8 bytes in length...; Jacktang Wireless Connectivity

FPGA Implementation of ECT Image Reconstruction Algorithm: ...; 至芯科技FPGA大牛 FPGA/CPLD

Why does the AD21 shortcut key not work after modification?: AD21 I changed the * key for drilling holes during wiring to 4. There is no conflict with other shortcut keys, but it does not work after the modification. When I press 4 during wiring, the hole will ...; dianhang PCB Design

[ESP32-Audio-Kit Audio Development Board Review] Basic Use of the Development Board: [i=s]This post was last edited by jinglixixi on 2021-9-25 10:12[/i]On the ESP32-Audio-Kit audio development board, the most basic peripherals are LED and KEY, and their schematic diagram is shown in F...; jinglixixi RF/Wirelessly

Can the SSTX and SSRX of USB3.0 be identified and adjusted? Is it necessary to cross it when making a schematic diagram?: Can the SSTX and SSRX of USB3.0 be identified and adjusted? Is it necessary to cross-process when making a schematic diagram?...; adherevictor PCB Design

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components