A29160UG-55F/Q datasheet, PDF - EEWORLD Datasheet

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A29160UG-55F/Q: DescriptionFlash, 1MX16, 55ns, PBGA48; Categorystorage storage; File Size528KB，45 Pages; ManufacturerAMICC [AMIC TECHNOLOGY]; Environmental Compliance

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A29160UG-55F/Q Overview

Flash, 1MX16, 55ns, PBGA48

A29160UG-55F/Q Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	AMICC [AMIC TECHNOLOGY]
package instruction	FBGA, BGA48,6X8,32
Reach Compliance Code	unknown
Maximum access time	55 ns
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B48
memory density	16777216 bit
Memory IC Type	FLASH
memory width	16
Number of departments/size	1,2,1,31
Number of terminals	48
word count	1048576 words
character code	1000000
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX16
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA48,6X8,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
ready/busy	YES
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.05 mA
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE

A29160UG-55F/Q Preview

A29160 Series

2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

Document Title

2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No.

0.0

0.1

0.2

History

Initial issue

Add

to TSOP and TFBGA package

Modify the pin configuration error of TFBGA

Modify the error of CFI codes of VCC Max, VCC Min, and minor version

Update byte mode, word mode program time, sector and chip erase time;

typical word mode active read current chart

Add Part Numbering Scheme

Issue Date

July 13, 2009

November 30, 2009

April 7, 2010

Remark

Preliminary

0.3

Page 1: Change from typical 100,000 cycles to minimum 100,000 cycles

November 25, 2010

(November, 2010, Version 0.3)

AMIC Technology, Corp.

A29160 Series

2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

Features

Single power supply operation

- Full voltage range: 4.5 to 5.5 volt for read and write

operations

Access times:

- 55/70 (max.)

Current:

- 20 mA typical active read current

- 30 mA typical program/erase current

0.5uA typical CMOS standby (

= VCC or Float)

Flexible sector architecture

16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors

8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:

A hardware method of protecting sectors to prevent any

inadvertent program or erase operations within that

sector. Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Unlock Bypass Program Command

- Reduces overall programming time when issuing

multiple program command sequence

Top or bottom boot block configurations available

Embedded Algorithms

- Embedded Erase algorithm will automatically erase the

entire chip or any combination of designated sectors and

verify the erased sectors

- Embedded Program algorithm automatically writes and

verifies data at specified addresses

Minimum 100,000 program/erase cycles per sector

20-year data retention at 125°C

Reliable operation for the life of the system

CFI (Common Flash Interface) compliant

- Provides device-specific information to the system,

allowing host software to easily reconfigure for different

Flash devices

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-supply

Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion of

program or erase operations

Ready /

BUSY

pin (RY /

)

- Provides a hardware method of detecting completion of

program or erase operations (not available on 44-pin

SOP)

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from, or

program data to, a non-erasing sector, then resumes the

erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array

data

input pin (48 pins TSOP, TFBGA)

- At V

, protects the 16Kbyte boot sector from erasure

regardless of sector protect/unprotect status.

- At V

, allows removal of boot sector protection.

Package options

44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA

All Pb-free (Lead-free) products are RoHS compliant

General Description

The A29160 is a 16Mbit, 5.0 volt-only Flash memory

organized as 2,097,152 bytes of 8 bits or 1,048,576 words of

16 bits each. The 8 bits of data appear on I/O

- I/O

; the 16

bits of data appear on I/O

~I/O

. The is offered in 48-ball

FBGA, 44-pin SOP and 48-Pin TSOP packages. This device

is designed to be programmed in-system with the standard

system 5.0 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However,

the A29160 can also be programmed in standard EPROM

programmers.

The A29160 has the first toggle bit, I/O

, which indicates

whether an Embedded Program or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O

toggle bit, the

A29160 has a second toggle bit, I/O

, to indicate whether the

addressed sector is being selected for erase. The A29160

also offers the ability to program in the Erase Suspend mode.

The standard A29160 offers access times of 55 and 70,

allowing high-speed microprocessors to operate without wait

states. To eliminate bus contention the device has separate

chip enable (

), write enable (

) and output enable

(

) controls.

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29160 is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

(November, 2010, Version 0.3)

AMIC Technology, Corp.

A29160 Series

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two

write cycles to program data instead of four.

The host system can detect whether a program or erase

operation is complete by observing the RY /

pin, or by

reading the I/O

(

Data

Polling) and I/O

(toggle) status bits.

After a program or erase cycle has been completed, the

device is ready to read array data or accept another

command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data

contents of other sectors. The A29160 is fully erased when

shipped from the factory.

The hardware sector protection feature disables operations

for both program and erase in any combination of the

sectors of memory. This can be achieved via programming

equipment.

The Write Protect (

) features protects the 16 Kbyte boot

sector from erasure by asserting a logic low on the

pin,

whether or not the sector had been previously protected.

The Erase Suspend/Erase Resume feature enables the user

to put erase on hold for any period of time to read data from,

or program data to, any other sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware

RESET

pin terminates any operation in

progress and resets the internal state machine to reading

array data. The

RESET

pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up

firmware from the Flash memory.

The device offers power-saving features. The system can

place the device into the standby mode. Power consumption

is greatly reduced in the standby modes.

Pin Configurations

SOP

RESET

A18

A17

VSS

I/O

A19

A10

A11

A12

A13

A14

A15

A16

BYTE

VSS

I/O

(A-1)

I/O

VCC

A15

A14

A13

A12

A11

A10

A19

RESET

RY/BY

A18

A17

A16

BYTE

VSS

I/O

(A-1)

I/O

VCC

I/O

VSS

TSOP (I)

A29160M

A29160V

(November, 2010, Version 0.3)

AMIC Technology, Corp.

A29160 Series

Pin Configurations (continued)

(November, 2010, Version 0.3)

AMIC Technology, Corp.

A29160 Series

Block Diagram

RY/BY

VCC

VSS

I/O

- I/O

(A-1)

Sector Switches

Erase Voltage

Generator

State

Control

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

Input/Output

Buffers

RESET

BYTE

Command

STB

VCC Detector

Timer

Y-Decoder

Y-Gating

Address Latch

A0-A19

X-decoder

Cell Matrix

Pin Descriptions

Pin No.

A0 - A19

I/O

- I/O

I/O

-1

)

-1

Description

Address Inputs

Data Inputs/Outputs

Data Input/Output, Word Mode

LSB Address Input, Byte Mode

Chip Enable

Write Enable

Write Protection

Output Enable

Hardware Reset

Selects Byte Mode or Word Mode

Ready/

BUSY

- Output

Ground

Power Supply

Pin not connected internally

RESET

BYTE

RY/

VSS

VCC

(November, 2010, Version 0.3)

AMIC Technology, Corp.

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Description	Flash, 1MX16, 55ns, PBGA48	Flash, 1MX16, 55ns, PDSO48	Flash, 1MX16, 70ns, PBGA48	Flash, 1MX16, 55ns, PBGA48	Flash, 1MX16, 70ns, PDSO44	Flash, 1MX16, 70ns, PBGA48	Flash, 1MX16, 55ns, PDSO48	Flash, 1MX16, 70ns, PDSO48
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]	AMICC [AMIC TECHNOLOGY]
package instruction	FBGA, BGA48,6X8,32	TSSOP, TSSOP48,.8,20	FBGA, BGA48,6X8,32	FBGA, BGA48,6X8,32	SOP, SOP44,.63	FBGA, BGA48,6X8,32	TSSOP, TSSOP48,.8,20	TSSOP, TSSOP48,.8,20
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Maximum access time	55 ns	55 ns	70 ns	55 ns	70 ns	70 ns	55 ns	70 ns
Spare memory width	8	8	8	8	8	8	8	8
startup block	BOTTOM	BOTTOM	TOP	TOP	BOTTOM	BOTTOM	TOP	BOTTOM
command user interface	YES	YES	YES	YES	YES	YES	YES	YES
Universal Flash Interface	YES	YES	YES	YES	YES	YES	YES	YES
Data polling	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	R-PBGA-B48	R-PDSO-G48	R-PBGA-B48	R-PBGA-B48	R-PDSO-G44	R-PBGA-B48	R-PDSO-G48	R-PDSO-G48
memory density	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	16	16	16	16	16	16	16	16
Number of departments/size	1,2,1,31	1,2,1,31	1,2,1,31	1,2,1,31	1,2,1,31	1,2,1,31	1,2,1,31	1,2,1,31
Number of terminals	48	48	48	48	44	48	48	48
word count	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000	1000000	1000000	1000000	1000000	1000000
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	85 °C	85 °C	70 °C	70 °C
organize	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FBGA	TSSOP	FBGA	FBGA	SOP	FBGA	TSSOP	TSSOP
Encapsulate equivalent code	BGA48,6X8,32	TSSOP48,.8,20	BGA48,6X8,32	BGA48,6X8,32	SOP44,.63	BGA48,6X8,32	TSSOP48,.8,20	TSSOP48,.8,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	SMALL OUTLINE	GRID ARRAY, FINE PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Department size	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K	16K,8K,32K,64K
Maximum standby current	0.000005 A	0.000005 A	0.000005 A	0.000005 A	0.000005 A	0.000005 A	0.000005 A	0.000005 A
Maximum slew rate	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	GULL WING	BALL	BALL	GULL WING	BALL	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.8 mm	0.8 mm	1.27 mm	0.8 mm	0.5 mm	0.5 mm
Terminal location	BOTTOM	DUAL	BOTTOM	BOTTOM	DUAL	BOTTOM	DUAL	DUAL
switch bit	YES	YES	YES	YES	YES	YES	YES	YES
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
ready/busy	YES	YES	YES	YES	-	YES	YES	YES

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