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JANTXVF2N7425

Description
Transistor
CategoryDiscrete semiconductor    The transistor   
File Size238KB,22 Pages
ManufacturerInfineon
Websitehttp://www.infineon.com/
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JANTXVF2N7425 Overview

Transistor

JANTXVF2N7425 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerInfineon
Reach Compliance Codeunknown
ConfigurationSingle
Maximum drain current (Abs) (ID)35 A
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-609 codee0
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Polarity/channel typeP-CHANNEL
Maximum power dissipation(Abs)3 W
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
The documentation and process conversion measures
necessary to comply with this document shall be
completed by 6 February 2014.
INCH-POUND
MIL-PRF-19500/660E
6 December 2013
SUPERSEDING
MIL-PRF-19500/660D
11 February 2013
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED
TRANSISTOR, P-CHANNEL SILICON, TYPES 2N7424, 2N7425, AND 2N7426,
JANTXVR, JANTXVF, JANSR, AND JANSF
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and
MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for a P-channel, enhancement-mode,
MOSFET, radiation hardened, power transistor. Two levels of product assurance are provided for each device type
as specified in
MIL-PRF-19500,
with avalanche energy maximum rating (E
AS
) and maximum avalanche current (I
AS
).
See
6.5
for JANHC and JANKC die versions.
1.2 Physical dimensions. See
figure 1,
TO-254AA.
1.3 Maximum ratings. Unless otherwise specified, T
A
= +25 C.
Type
P
T
(1)
T
C
=
+25°C
W
2N7424
2N7425
2N7426
250
250
250
P
T
T
A
=
+25°C
W
3.0
3.0
3.0
R
θJC
(2)
V
DS
V
DG
V
GS
I
D1
(3) (4)
T
C
=+25°C
I
D2
(3)(4)
T
C
=
+100°C
A dc
-30
-24
-17
I
S
I
DM
(5)
T
J
and
T
STG
°C
-55
to
+150
o
°C/W
0.50
0.50
0.50
V dc
-60
-100
-200
V dc
-60
-100
-200
V dc
±20
±20
±20
A dc
-35
-35
-27
A dc
-35
-35
-27
A (pk)
-140
-140
-108
(1)
(2)
(3)
Derate linearly 2.0 W/°C for T
C
> +25°C.
See
figure 2,
thermal impedance curves.
The following formula derives the maximum theoretical I
D
limit. I
D
is limited by package and internal
construction.
T
JM
- T
C
I
D
=
(
R
θ
JC
)
x
(
R
DS
( on ) at T
JM
)
See
figure 3,
maximum drain current graphs.
I
DM
= 4 x I
D1
as calculated in note 3.
(4)
(5)
Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to
Semiconductor@dla.mil.
Since contact
information can change, you may want to verify the currency of this address information using the ASSIST
Online database at
https://assist.dla.mil.
AMSC N/A
FSC 5961

JANTXVF2N7425 Related Products

JANTXVF2N7425 JANSF2N7424 JANTXVF2N7424
Description Transistor Power Field-Effect Transistor, 35A I(D), 60V, 0.053ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA, HERMETIC SEALED, CERAMIC PACKAGE-3 Power Field-Effect Transistor, 35A I(D), 60V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-254AA, TO-254AA, 3 PIN
Is it Rohs certified? incompatible incompatible incompatible
Maker Infineon Infineon Infineon
Reach Compliance Code unknown unknown unknown
Configuration Single SINGLE WITH BUILT-IN DIODE SINGLE
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-609 code e0 e0 e0
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Polarity/channel type P-CHANNEL P-CHANNEL P-CHANNEL
surface mount NO NO NO
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
package instruction - HERMETIC SEALED, CERAMIC PACKAGE-3 TO-254AA, 3 PIN
ECCN code - EAR99 EAR99
Other features - HIGH RELIABILITY RADIATION HARDENED
Avalanche Energy Efficiency Rating (Eas) - 500 mJ 500 mJ
Minimum drain-source breakdown voltage - 60 V 60 V
Maximum drain current (ID) - 35 A 35 A
JEDEC-95 code - TO-254AA TO-254AA
JESD-30 code - S-CSFM-P3 S-XSFM-P3
Number of components - 1 1
Number of terminals - 3 3
Package body material - CERAMIC, METAL-SEALED COFIRED UNSPECIFIED
Package shape - SQUARE SQUARE
Package form - FLANGE MOUNT FLANGE MOUNT
Peak Reflow Temperature (Celsius) - NOT SPECIFIED NOT SPECIFIED
Maximum pulsed drain current (IDM) - 140 A 192 A
Certification status - Qualified Qualified
Guideline - MIL-19500/660 MIL-19500/660A
Terminal form - PIN/PEG PIN/PEG
Terminal location - SINGLE SINGLE
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED
Transistor component materials - SILICON SILICON
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