GS815018AGB-300T datasheet, PDF

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GS815018AGB-300T: DescriptionLate-Write SRAM, 1MX18, 1.6ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119; Categorystorage storage; File Size615KB，25 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS815018AGB-300T Overview

Late-Write SRAM, 1MX18, 1.6ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119

GS815018AGB-300T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	1.6 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	18874368 bit
Memory IC Type	LATE-WRITE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.99 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS815018/36AB-357/333/300/250

119-Bump BGA

Commercial Temp

Industrial Temp

Features

• Register-Register Late Write mode, Pipelined Read mode

• 2.5 V +200/–200 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• ZQ controlled programmable output drivers

• Dual Cycle Deselect

• Fully coherent read and write pipelines

• Byte write operation (9-bit bytes)

• Differential HSTL clock inputs, K and K

• Asynchronous output enable

• Sleep mode via ZZ

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• JEDEC-standard 119-bump BGA package

• RoHS-compliant 119-bump BGA package available

1M x 18, 512K x 36

18Mb Register-Register Late Write SRAM

Functional Description

250 MHz–357 MHz

2.5 V V

1.5 V or 1.8 V HSTL I/O

Because GS815018/36A are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

GS815018/36A support pipelined reads utilizing a rising-edge-

triggered output register. They also utilize a Dual Cycle

Deselect (DCD) output deselect protocol.

GS815018/36A are implemented with high performance HSTL

technology and are packaged in a 119-bump BGA.

Family Overview

GS815018/36A are 18,874,368-bit (18Mb) high performance

SRAMs. This family of wide, low voltage HSTL I/O SRAMs

is designed to operate at the speeds needed to implement

economical high performance cache systems.

Mode Control

There are two mode control select pins (M1 and M2), which

allow the user to set the correct read protocol for the design.

The GS815018/36A support single clock Pipeline mode, which

directly affects the two mode control select pins. In order for

the part to fuction correctly, and as specified, M1 must be tied

to V

and M2 must be tied to V

or V

DDQ

. This must be set

at power-up and should not be changed during operation.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Parameter Synopsis

-357

Pipeline

Cycle

tKHQV

Curr (x18)

Curr (x36)

2.8

1.4

600

650

-333

3.0

1.5

550

600

-300

3.3

1.6

500

550

-250

4.0

2.0

450

500

Unit

Rev: 1.08 9/2008

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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