®
S E M I C O N D U C T O R S
MUSIC
I
MU9C8248
FDDI SRT Interface
PRELIMINARY DATA SHEET
DISTINCTIVE CHARACTERISTICS
• High-speed FDDI Source Routing and Transparent
Bridging address filter supports up to sixteen ports
• Glue-free operation with the MUSIC MU9C1480 LANCAM
and AMD, National Semiconductor, and Motorola FDDI
chip sets
• Configurable for both Motorola and Intel processor
addressing modes
• Complies with the ISO 9314 standard for FDDI
• 64-entry Instruction Buffer holds up to six down-
loadable filtering and purging routines
• 64-entry Data Buffer or internal FIFO
• Automatic selection of Source Routing or Transparent
filtering routines based on Transceiver output data
• Supplies proper XDAMAT, XSAMAT, SRMAT, ABORT,
and CIP signals to the FDDI chip sets
• Selectable filtering options for each frame type
• Checks validity of Routing Information Field
• TTL-compatible interfaces
• Manufactured in CMOS technology
• Available in 100-pin PQFP package
GENERAL DESCRIPTION
The MU9C8248 is a Source Routing Transparent (SRT) Interface to the
MUSIC Semiconductors LANCAM for use in FDDI LAN Bridges and
Brouters. This interface operates in accordance with ISO standards
while supporting address filtering rates up to 500,000 frames/sec for
minimum-length frames.
The MU9C8248 has five interfaces to provide “glue-free” address
filtering. The Transceiver interface monitors receive data between the
Physical Layer device and the MAC and determines whether to filter
according to Source Routing or Transparent Bridging standards. The
MAC interface supplies signals to instruct the FDDI chip set to reject or
copy a frame. The LANCAM interface controls the companion
LANCAM(s) for Transparent filtering. The Host Processor interface
allows direct initialization of the MU9C8248, and downloading of the
filtering and purging routines. The FIFO interface outputs new
addresses received from the FDDI network.
The MU9C8248 can choose to copy or reject a frame depending on the
frame's DA, RIF, and/or the frame type (MAC, LLC, or Reserved), and
can perform multiple validity checks within the Routing Information
Field (RIF), including general checks on every Routing Control Field
(RCF) as well as multiple frame related checks.
The internal RAM can store up to 64 instructions at initialization for the
LANCAM to execute matching, learning, aging, and purging operations.
Up to six routines can be stored here and started by the network or the
Node Processor. Internal arbitration prioritizes execution of instructions
by the LANCAM. A second internal RAM, which contains 64 16-bit
words, is used for data buffering operations or as an internal FIFO.
With sixteen Ring-Bridge-Ring number combinations stored internally,
the MU9C8248 is very well suited to operate as an address filter in
multi-port Source Routing Bridge/Brouter environments.
BLOCK DIAGRAM
RCDAT7-
RCDAT0
RCCONT,
RCCONTA
RCCONTB
XDAMAT
XSAMAT
PARITY
SRMAT
ABORT
CIP
8
TRANSCEIVER
INTERFACE
MAC
INTERFACE
/INT
6
TRANSPARENT
BRIDGING BLOCK
LANCAM INTERFACE
HOST PROCESSOR
INTERFACE
16
A5-A0
D15-D0
ALE, SRNW
/CS
/RS, /LDS
/WS, /UDS
/HBRDY
/HBEN
/HBDIR
/RESET
8
/FULL, /EMPTY
DF7-DF0
MCLK
/WF
DFC
/FFI
/INTEL
DCLK
STRIP
STOP STRIP
DQ15-DQ0
16
/E
/W
/CM
/EC
/MI
/FI
SOURCE ROUTING
BLOCK
INSTRUCTION
BUFFER
ARBITER
MUSIC is a trademark of MUSIC Semiconductors. LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of
MUSIC Semiconductors. AMD is a registered trademark of Advanced Micro Devices, Inc. National Semiconductor is a registered trademark of National
Semiconductor Corporation. Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation.
15 April 1997 Rev. 2.5
Web
MU9C8248
PINOUT DIAGRAM
SRMAT
ABORT
VCC
ALE, SRNW
/CS
GND
/RS, /LDS
/WS, /UDS
D0
D1
D2
D3
D4
D5
D6
D7
VCC
D8
D9
GND
D10
D11
D12
D13
D14
D15
VCC
/HBRDY
/HBEN
GND
XSAMAT
GND
XDAMAT
CIP
VCC
/EC
/CM
/FI
/MI
GND
/E
/W
VCC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MU9C8248
FDDI Interface
(Top View)
/HBDIR
A0
A1
A2
A3
A4
A5
/RESET
/INTEL
/INT
/FULL, /EMPTY
DF7
DF6
DF5
DF4
DF3
DF2
DF1
DF0
DFC
LANCAM Interface:
DQ15–DQ0
(Data Bus, Common I/O, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8248 and the LANCAM. The direction and
nature of the information that flows between the devices are
determined by the states of /CM and /W.
/E
(Chip Enable, Output, TTL)
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
/W
(Write Enable, Output, TTL)
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
Rev. 2.5
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DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DCLK
RCDAT0
RCDAT1
RCDAT2
RCDAT3
RCDAT4
RCDAT5
GND
RCDAT6
RCDAT7
VCC
RCCONT, RCCONTA
RCCONTB
PARITY
MCLK
STRIP
STOPSTRIP
WF
/FFI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PIN DESCRIPTIONS
(/X indicates an active LOW function)
/CM (Data/Command Select, Output, TTL)
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
/EC (Enable Comparison, Output, TTL)
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
/MI (Match Flag, Input, TTL)
The LANCAM /MF pin takes the MU9C8248's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8248's routines and signalling
to the FDDI chipset.
MU9C8248
PIN DESCRIPTIONS (CONT’D)
/FI
(Full Flag, Input, TTL)
DCLK (Data Clock, Input, TTL)
The rising edge of DCLK clocks the RCDAT7-RCDAT0 data,
RCCONT, RCCONTA , RCCONTB and PARITY received from
the Physical layer device, which composed this data out of the
data received from the FDDI network.
The /FI input will be driven LOW by the LANCAM /FF output pin
if all the LANCAM memory locations have valid contents. The
status of the /FI pin can be read by the Host processor from the
MU9C8248's Control register and is also used to prevent
learning of new network addresses.
Transceiver Interface:
RCDAT7-RCDAT0 (Receive Data, Input, TTL)
The RCDAT pins monitor the data received by the Physical
layer device from the FDDI network. RCDAT7-RCDAT0 are
clocked on the rising edge of DCLK. The first symbol received
from the fiber is placed on RCDAT7-RCDAT4 whereby the first
bit received from the fiber is placed on RCDAT7. For chipsets
using two associated Receive Data Control bits, each four-bit
symbol has an associated RCCONT bit to indicate whether the
four-bit symbol is to be considered a Data symbol or a Control
symbol. RCCONT B is associated with RCDAT7-RCDAT4 and
RCCONT A is associated with RCDAT3-RCDAT0. For chipsets
using one associated Receive Data Control bit, RCCONT A
becomes RCCONT and is the indicator for both symbols.
MAC Interface:
XDAMAT
(External Destination Address Match,
Output, Three-state TTL)
XDAMAT indicates, when made active, the FDDI chipset to
copy a FDDI frame (this decision is made on basis of the
Destination Address of the frame currently being received). The
duration and polarity of XDAMAT are set in the Transparent
Bridging/MAC register.
XSAMAT
(External Source Address Match,
Output, Three-state TTL)
RCCONT A or RCCONT
(Receive Data Control
Bit, Input, TTL)
XSAMAT, when active, indicates that the Source Address of
the frame currently being received is found in the LANCAM
database. The duration and polarity of XSAMAT are set in the
Transparent Bridging/MAC register.
For chipsets providing two Receive Data Control bits, RCCONT
A is associated with RCDAT3-RCDAT0 to indicate that the
four-bit symbol being presented on RCDAT3-RCDAT0 is a
Control symbol (RCCONT A is HIGH) or a Data symbol
(RCCONT A is LOW).
For chipsets using only one Control bit for each symbol pair,
RCCONT A becomes RCCONT and is the only Receive Data
Control bit used. If RCCONT is HIGH, both RCDAT7-RCDAT4
and RCDAT3-RCDAT0 are Control symbols. If RCCONT is
LOW, both RCDAT7-RCDAT4 and RCDAT3-RCDAT0 are Data
symbols. RCCONT A or RCCONT is valid on the rising edge of
DCLK.
SRMAT (Source Routing Match, Output,
Three-state TTL)
SRMAT, when active, indicates that the frame currently being
received should be copied and forwarded based on information
in the Routing Information Field of that frame. The duration and
polarity of SRMAT are set in the Transparent Bridging/MAC
register.
ABORT (Abort, Output, Three-state TTL)
ABORT is used to notify the FDDI chipset that the frame
currently being received should not be copied and forwarded.
The duration and polarity of ABORT are set in the Transparent
Bridging/MAC register.
RCCONT B
(Receive Data Control Bit, Input, TTL)
CIP (Compare in Progress, Output, TTL)
CIP is an output signal that National Semiconductors needs to
notify their system interface that a Compare is in Progress.
CIP goes HIGH on the third rising edge of DCLK after the edge
that loaded a valid FC field into the MU9C8248. CIP returns
LOW on the seventh rising edge of DCLK after the last byte of
the Source Address field for frames not containing a Routing
Information Field (RIF), or on the seventh rising edge of DCLK
after the last byte of the RIF, if the frame contains such a field.
RCCONT B is provided by the Physical layer devices, is valid
on the rising edge of DCLK, and is used to indicate that the
four-bit symbol being presented on RCDAT7-RCDAT4 is a
Control symbol (RCCONT B is HIGH) or a Data symbol
(RCCONT B is LOW). For FDDI chipsets which use only one
control bit RCCONT B should be tied to GND.
PARITY
(Parity, Input, TTL)
This input signal is the ODD parity of the RCDAT bus and
RCCONT when the MU9C8248 is used in National
Semiconductors (NS) mode. It is the ODD parity of the RCDAT
bus and RCCONT A and -B when the MU9C8248 is
programmed in not NS mode.
Rev. 2.5
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MU9C8248
PIN DESCRIPTIONS (CONT’D)
Host Processor Interface:
ALE, SRNW
(Address Latch Enable/System Read
Not Write, Input, TTL)
/RS, /WS, or /LDS and /UDS HIGH, the MU9C8248 takes
/HBRDY HIGH. /HBRDY becomes three-state one MCLK
period later.
/HBEN
(Data Buffer Enable, Output, TTL)
This pin is ALE when the MU9C8248 is used in the Intel mode.
A positive pulse on ALE latches the address from the
multiplexed data/address lines. If the MU9C8248 is in the
Motorola mode, this pin becomes SRNW, and is HIGH for a
Host Processor Read cycle and LOW for a Write cycle.
If external bi-directional buffers are needed on the D15–D0
lines, /HBEN goes LOW to enable the external buffers. /HBEN
goes HIGH to disable the external buffers.
/HBDIR
(Data Buffer Direction, Output, TTL)
/CS
(Chip Select, Input, TTL)
/CS going LOW enables the Host Processor interface of the
MU9C8248 for a Host Processor read or write. When /CS is
HIGH, the Host Processor interface is not active.
/HBDIR controls the direction of external bi-directional buffers.
/HBDIR goes LOW to read from the registers of the MU9C8248
and HIGH to write to the MU9C8248 registers.
External FIFO Interface:
DF7-DF0
(FIFO data, Output, TTL)
A5–A0
(Address, Input, TTL)
The Address pins select the internal register for Host processor
reads and writes. Depending on the Processor interface, the
Address pins are latched by a positive pulse on ALE, or must
remain stable until the rising edge of /RS, /WS, or /LDS and
/UDS, as shown in the Timing diagrams.
On the rising edge of /WF, DF7-DF0 contain a part of a new
Source Address (SA), which is just learned by the LANCAM.
This new SA is written into an external FIFO connected to
these DF7-DF0 in six cycles.
D15–D0
(Data, Common I/O, TTL)
DFC
(FIFO Control data, Output, TTL)
The Data pins transfer data between the Host Processor and
the internal registers of the MU9C8248. Depending on the
Processor Interface, the data pins are registered on the rising
edge of /WS, or /LDS and /UDS; or must remain stable until the
rising edge of /RS, or /LDS and /UDS, as shown in the Timing
diagrams.
On the rising edge of /WF, DFC indicates whether the part of
the new SA present on DF7-DF0 is the first part of this SA. If
this is the first of the six write cycles DFC is HIGH. For the
other five cycles, DFC is LOW.
/WF
(FIFO Write, Output, TTL)
/RS, /LDS
(Read Strobe/Lower Data Strobe,
Input, TTL)
On the rising edge of /WF, data on DF7-DF0 and DFC is
present and can be written to e.g. an external FIFO.
If the MU9C8248 is used in the Intel mode, this pin is /RS and
goes LOW to begin a read cycle to the Host Processor
interface. If the MU9C8248 is used in the Motorola mode, this
pin is /LDS for Host processor read and write cycles and should
be asserted in combination with /UDS. Data is read by the Host
processor on the rising edge of /RS or /LDS, or is written into
the MU9C8248 on the rising edge of /LDS.
/FFI
(FIFO Full, Input, TTL)
When /FFI is LOW, the MU9C8248 is indicated that the
external FIFO is full and can't accept new SAs. Learning of new
SAs in the LANCAM is then also disabled. When /FFI is HIGH
learning of new SAs both in the external FIFO and LANCAM is
enabled.
/WS, /UDS
(Write Strobe/Upper Data Strobe,
Input, TTL)
Miscellaneous:
/RESET
(Hardware Reset, Input, TTL)
If the MU9C8248 is used in the Intel mode, this pin is /WS, and
goes LOW to begin a write cycle from the Host Processor
interface. If the MU9C8248 is used in the Motorola mode, this
pin is /UDS for Host processor read and write actions and
should be asserted in combination with /LDS. Data is written
into the MU9C8248 on the rising edge of /WS or /UDS, or is
read from the MU9C8248 on the rising edge of /UDS.
Taking /RESET LOW for at least 1 MCLK cycle sets the
MU9C8248 to a predefined state. The contents of all registers
are 0000H after a Hardware reset.
/INT
(Interrupt, Output, Open Drain)
/HBRDY
(Ready, Output, Three-state TTL)
/HBRDY goes LOW to indicate to the Host processor that a
data transfer is completed. After the Host processor has made
This pin goes LOW to notify the Host processor that the
MU9C8248 is accessing the LANCAM. /INT is synchronized on
/HBRDY and becomes active directly if no Host Processor
LANCAM access cycle is active or after a possible pending
Host Processor LANCAM access cycle has been completed
(/HBRDY is HIGH) succesfully.
Rev. 2.5
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MU9C8248
PIN DESCRIPTIONS (CONT’D)
/FULL, /EMPTY
(Full/Empty, Output, Open Drain)
If part of the Instruction buffer in the MU9C8248 is configured
as a FIFO, this active-LOW pin can be configured to signal
whether the FIFO is full (all entries contain valid data) or empty
(no entry contains data). The definition of this signal is
programmed in the FIFO Control/Delay register.
STRIP is the overrulling signal which means that if STRIP is
continuously kept HIGH, the assertion of STOP STRIP or the
reception of a void frame or token doesn't enable the signalling
and learning features of the MU9C8248.
STOP STRIP
(Stop Strip, Input, TTL)
/INTEL
(HPI Selection, Input, TTL)
The /INTEL pin identifies which type of microcontroller is
connected to the Host Processor interface. This pin is set LOW
for Intel-type addressing modes and HIGH for Motorola-type
addressing modes.
When STOP STRIP has been asserted for one MCLK period
after STRIP has been HIGH for at least one MCLK period (and
STRIP is LOW now), the MU9C8248 stops stripping and
enables signalling and learning for the next FDDI frame.
MCLK
(Master Clock, Input, TTL)
STRIP
(Strip, Input, TTL)
MCLK is the 25 MHz master clock. MCLK is used to clock all
system parts of the MU9C8248.
When STRIP has been asserted HIGH for only one MCLK
period and STOP STRIP is kept LOW, the MU9C8248 stops
the execution of the Routines 0 and 1 for the next FDDI frame.
The result is that no signalling on the MAC interface and SA
learning takes place. After STOP STRIP has been asserted for
one MCLK period or any token or void frame has been
received, signalling and learning is enabled again for the next
FDDI frame.
VCC, GND
(Positive Power Supply and Ground)
These pins are the main power supply connections to the
MU9C8148. VCC must be held at +5V ± 10% relative to the
GND pin, which is at 0V (system reference potential), for
correct operation of the device.
FUNCTIONAL DESCRIPTION
Referring to the Block diagram shown on Page 1, the
MU9C8248 consists of four functional blocks: the Transparent
Bridging Block (TBB) , the Source Routing Block (SRB), the
Instruction/Data Buffer (IB), and the Arbiter. Five interfaces
connect the MU9C8248 to the FDDI Physical Layer device, the
MAC controller or System interface, the Host processor, an
external FIFO and the LANCAM. For a detailed description of
FDDI frames, refer to the ISO9314-2 Standard.
The FC field indicates whether the current frame is a Token or
a regular frame. If a Token (Restricted or Non Restricted) is
being received the TBB discards it, thereby having the 8248 not
asserting any signals on the MAC interface. For a regular
frame, the bits in the Frame Control field signify the type of
frame (VOID, SMT, LLC, MAC, or Reserved) being received.
The TBB decides either to copy or discard the frame directly,
based on the settings in the Frame Type Selection register or
to filter on the DA.
Positive or negative filtering on the DA is selected by the
PONNE bit in the Transparent Bridging/MAC register. Filtering
on the DA is done on all frames except for VOID-, SMT- and
other types of frames with 16-bit addresses. No filtering and
signalling takes place for these frames.
Positive filtering implies that a frame should be forwarded if its
DA is found in the LANCAM address database. Routine 0 in the
instruction buffer examines the DA to determine whether a
frame should be copied or not. The results of this comparison
are used to notify the FDDI chip set to copy or discard the
frame. Negative filtering implies that a frame should be
forwarded if its DA is not found in the address database. In this
case, the MU9C8248 checks the DA and destinguishes
between MAC, Broadcast, Functional and Group addresses.
Based upon the settings of the Transparent Bridging/MAC
register, the TBB discards a frame whose DA is either a
Broadcast, Functional and/or Group address.
Transparent Bridging Block
For all frames which do not contain a Routing Information Field
(RIF), the TBB makes decisions whether to copy or discard a
frame based on the Destination address (DA) and the Frame
Control field (FC). If the MU9C8248 is not used in a
Transparent Bridging Only mode and a frame containing an
RIF is received the Source Routing Block performs the filtering
actions and no DA comparison takes place. If the bridge is set
for Transparent Bridging Only (the TBO bit in the Control
register is HIGH), the TBB also makes copy or discard
decisions (based on DA and/or FC) for frames which do contain
an RIF.
The TBB parses the data as received from the Physical Layer
device off the FDDI network, and indicates to the MAC
interface whether to assert the XDAMAT, XSAMAT, ABORT
and CIP signals. For each frame, the TBB examines the Frame
Control field (FC), the Destination address (DA), and the
Source address (SA), which contains the Routing Information
indicator (RII). If this RII is HIGH that frame contains a RIF.
Rev. 2.5
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