TC74VCXHR162652FT(EL) datasheet, PDF

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TC74VCXHR162652FT(EL): DescriptionTC74VCXHR162652FT(EL); Categorylogic logic; File Size250KB，15 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC74VCXHR162652FT(EL) Overview

TC74VCXHR162652FT(EL)

TC74VCXHR162652FT(EL) Parametric

Parameter Name	Attribute value
Maker	Toshiba Semiconductor
package instruction	TSSOP, TSSOP56,.3,20
Reach Compliance Code	unknown
Control type	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL
JESD-30 code	R-PDSO-G56
Load capacitance (CL)	30 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.012 A
Number of digits	8
Number of functions	2
Number of terminals	56
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP56,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
power supply	3.3 V
Prop。Delay @ Nom-Sup	3.8 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE

TC74VCXHR162652FT(EL) Preview

TC74VCXHR162652FT

TOSHIBA CMOS Digital Integrated Circuit

Silicon Monolithic

TC74VCXHR162652FT

Low-Voltage 16-Bit Bus Transceiver/Register with Bushold

The TC74VCXHR162652FT is a high-performance CMOS

16-bit bus transceiver/register. Designed for use in 1.8-V, 2.5-V or

3.3-V systems, it achieves high-speed operation while

maintaining the CMOS low power dissipation.

This device is bus transceiver with 3-state outputs, D-type

flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the internal registers.

The 26-Ω series resistor helps reducing output overshoot and

undershoot without external resistor.

The A, B data inputs include active bushold circuitry,

Weight: 0.25 g (typ.)

eliminating the need for external pull-up resistors to hold unused

or floating data inputs at a valid logic level.

All inputs are equipped with protection circuits against static discharge.

Features (Note)

•

26-Ω series resistors on outputs

Low-voltage operation: V

= 1.8 to 3.6 V

Bushold on data inputs eliminating the need for external pull-up/pull-down resistors

High-speed operation : t

= 3.8 ns (max) (V

= 3.0 to 3.6 V)

: t

= 4.9 ns (max) (V

= 2.3 to 2.7 V)

: t

= 9.8 ns (max) (V

= 1.8 V)

•

3.6-V tolerant control inputs

Output current : I

= ±12 mA (min) (V

= 3.0 V)

: I

= ±8 mA (min) (V

= 2.3 V)

: I

= ±4 mA (min) (V

= 1.8 V)

•

Latch-up performance:

−300

ESD performance: Machine model

≥ ±200

Human body model

≥ ±2000

Package: TSSOP

Note:

Do not apply a signal to any bus pins when it is in the output mode. Damage may result.

2007-10-19

TC74VCXHR162652FT

Pin Assignment

(top view)

IEC Logic Symbol

1OEAB

1CAB

1SAB

GND

1A1

1A2

1A3

1A4

1OEBA

1CBA

1SBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1OEBA

1OEAB

EN1 (BA)

EN2 (AB)

EN7 (BA)

EN8 (AB)

G10

C11

G12

1 4

1CBA

1SBA

1CAB

1SAB

2OEBA

2OEAB

2CBA

2SBA

2CAB

2SAB

1A1

1B1

4 1

1A5 10

GND 11

1A6 12

1A7 13

1A8 14

2A1 15

2A2 16

2A3 17

GND 18

2A4 19

2A5 20

2A6 21

2A7 23

2A8 24

GND 25

2SAB 26

2CAB 27

2OEAB 28

1A2

1A3

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

1B7

1B8

2B1

2B2

2B3

GND

1A8

2B4

2B5

2B6

2B7

2B8

GND

2SBA

2CBA

2A4

2A5

2A6

2A7

2A8

2A2

2A3

2A1

1A4

1A5

1A6

1A7

1 10

11D

1 12

2B2

2B3

2B4

2B5

2B6

2B7

2B8

2OEBA

2007-10-19

TC74VCXHR162652FT

Truth Table

Control Inputs

OEAB

Bus

SAB

SBA

Input

Output

Input

Output

Input

Output

The data in the A storage flop-flops are

displayed on the B Bus, and the data in the

B storage flop-flops are displayed on the A.

The data on the B Bus are displayed on the

A Bus, and are stored into the B storage

flip-flops on the rising edge of CBA.

The data in the B storage flip-flops are

displayed on the A Bus.

The data on the B Bus are stored into the B

storage flip-flops on the rising edge of CBA,

and the stored data propagate directly onto

the A Bus.

The data on the B Bus are displayed on the

A bus.

The data on the A bus are displayed on the

B Bus, and are stored into the A storage

flip-flops on the rising edge of CAB.

The data in the A storage flop-flops are

displayed on the B Bus.

The data on the A Bus are stored into the A

storage flip-flops on the rising edge of CAB,

and the stored data propagate directly onto

the B Bus.

The data on the A bus are displayed on the

B bus.

OEBA

CAB

CBA

Function

The output functions of A and B Busses are

disabled.

Both A and B Busses are used as inputs to

the internal flip-flops. Data on the Bus will be

stored on the rising edge of the Clock.

X: Don’t care

Z: High impedance

: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs.

The clocks are not internally gated with either OEAB or

OEBA

Therefore, data on the A and/or B busses may be clocked into the storage flip-flops at any time.

2007-10-19

TC74VCXHR162652FT

System Diagram

1OEAB

1OEBA

1A1

1B1

1A8

1CAB

1SAB

Same as above block

1B8

1CBA

1SBA

2OEAB

2OEBA

2A1

φA

φB

42 2B1

2A8

2CAB

2SAB

φA

Same as above block

φB

2B8

2CBA

2SBA

2007-10-19

TC74VCXHR162652FT

Timing Chart

OEAB

OEBA

SAB

SBA

CAB

CBA

A: Input

B: Output

A: Output

B: Input

: Don’t care

Absolute Maximum Ratings (Note 1)

Characteristics

Power supply voltage

DC input

voltage

output

voltage

Input diode current

Output diode current

Output current

Power dissipation

DC V

/ground current per supply pin

Storage temperature

(OEAB, OEBA , SAB,

SBA, CAB, CBA)

(An, Bn)

Symbol

Rating

−0.5

to 4.6

−0.5

to 4.6

−0.5

to V

0.5

(Note 2)

OUT

GND

stg

−0.5

to V

0.5

(Note 3)

−50

±50

400

±100

−65

to 150

(Note 4)

°C

Unit

(An, Bn)

Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or

even destruction.

Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the

significant change in temperature, etc.) may cause this product to decrease in the reliability significantly

even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute

maximum ratings and the operating ranges.

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook

(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test

report and estimated failure rate, etc).

Note 2: OFF state

Note 3: High or low state. I

OUT

absolute maximum rating must be observed.

Note 4: V

OUT

GND, V

OUT

2007-10-19

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