Features
•
•
•
•
•
Supply Voltage up to 40V
Operating Voltage V
S
= 5V to 27V
Typically 10 µA Supply Current During Sleep Mode
Typically 57 µA Supply Current in Silent Mode
Linear Low-drop Voltage Regulator:
– Normal, Fail-safe, and Silent Mode
– ATA6623: V
CC
= 3.3V ±2%
– ATA6625: V
CC
= 5.0V ±2%
– Sleep Mode: V
CC
is Switched Off
V
CC
Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)
Voltage Regulator is Short-circuit and Over-temperature Protected
LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2
Wake-up Capability via LIN Bus (90 µs Dominant)
TXD Time-out Timer
Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
Advanced EMC and ESD Performance
Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev1.0”
Interference and Damage Protection According to ISO7637
Package: SO8
•
•
•
•
•
•
•
•
•
•
LIN Bus
Transceiver
with Integrated
Voltage
Regulator
ATA6623
ATA6625
ATA6623C
ATA6625C
1. Description
ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0 and 2.1, with a low-drop voltage regulator (3.3V/5V/50 mA). The
combination of voltage regulator and bus transceiver makes it possible to develop
simple, but powerful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is
designed to handle the low-speed data communication in vehicles (for example, in
convenience electronics). Improved slope control at the LIN driver ensures secure
data communication up to 20 kBaud with an RC oscillator for the protocol handling.
The bus output is designed to withstand high voltage. Sleep Mode (voltage regulator
switched off) and Silent Mode (communication off; V
CC
voltage on) guarantee mini-
mized current consumption.
4957H–AUTO–05/10
Figure 1-1.
Block Diagram
ATA6623/25
V
CC
Normal
Mode
1
VS
RXD
5
Receiver
-
+
RF-filter
4
LIN
V
CC
Wake-up
bus
timer
Short
circuit
and
overtemperature
protection
TXD
6
TXD
Time-out
timer
Slew
rate control
8
EN
2
Sleep
mode
Control
VCC
unit
switched
off
Normal/Silent/
Fail-safe Mode
3.3V/50
mA/±2%
5V/50 mA/±2%
Undervoltage reset
7
VCC
NRES
GND
3
2. Pin Configuration
Figure 2-1.
Pinning SO8
VS
EN
GND
LIN
1
2
3
4
8
7
6
5
VCC
NRES
TXD
RXD
Table 2-1.
Pin
1
2
3
4
5
6
7
8
Pin Description
Symbol
VS
EN
GND
LIN
RXD
TXD
NRES
VCC
Function
Battery supply
Enables Normal Mode if the input is high
Ground, heat sink
LIN bus line input/output
Receive data output
Transmit data input
Output undervoltage reset, low at reset
Output voltage regulator 3.3V/5V/50 mA
2
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
3. Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all
nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer
nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any
restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is V
S
= 5V to 27V. An undervoltage detection is implemented to disable
transmission if V
S
falls below 5V, in order to avoid false bus messages. After switching on V
S
,
the IC starts with the Fail-safe Mode and the voltage regulator is switched on (i.e.,
3.3V/5V/50 mA).
The supply current in Sleep Mode is typically 10 µA and 57 µA in Silent Mode.
3.3
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a
ground shift up to 11.5% of V
S
.
3.4
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying
the microcontroller and other ICs on the PCB and is protected against overload by means of cur-
rent limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold V
thun
.
3.5
Undervoltage Reset Output (NRES)
If the V
CC
voltage falls below the undervoltage detection threshold of V
thun
, NRES switches to
low after tres_f (Figure
6-1 on page 11).
Even if V
CC
= 0V the NRES stays low, because it is
internally driven from the V
S
voltage. If V
S
voltage ramps down, NRES stays low until V
S
< 1.5V
and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for t
Reset
= 4 ms after V
CC
reaches its
nominal value.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal
pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from
–27V to +40V. This pin exhibits no reverse current from the LIN bus to V
S
, even in the event of a
GND shift or V
Batt
disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled.
3
4957H–AUTO–05/10
3.7
Input Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output.
TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected
(internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive
state.
3.8
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than t
DOM
> 6 ms, the
LIN bus driver is switched to the recessive state.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
3.9
Output Pin (RXD)
This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state)
is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD.
The output has an internal pull-up resistor with typically 5 kΩ to V
CC
. The AC characteristics are
measured with an external load capacitor of 20 pF.
The output is short-circuit protected. In Unpowered Mode (that is, V
S
= 0V), RXD is switched off.
3.10
Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in
Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The
VCC voltage regulator operates with 3.3V/5V/50 mA output capability.
If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data trans-
mission is then possible, and the current consumption is reduced to I
VS
typ. 57 µA. The VCC
regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmis-
sion is possible, and the voltage regulator is switched off.
4
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
4. Mode of Operation
Figure 4-1.
Mode of Operation
Unpowered Mode
V
Batt
= 0V
b
a
a: V
S
> 5V
b: V
S
< 4V
c: Bus wake-up event
d: NRES switches to low
Fail-safe Mode
b
d
EN = 1
Go to silent command
VCC:
3.3V/5V/50 mA
with undervoltage monitoring
Communication:
OFF
EN = 1
c
b
c+d
b
Silent Mode
EN = 0
TXD = 1
Normal Mode
VCC:
3.3V/5V/50 mA
with undervoltage
monitoring
EN = 0
Communication:
ON
TXD = 0
Sleep Mode
Local wake-up event
EN = 1
VCC:
3.3V/5V/50 mA
with undervoltage monitoring
Communication:
OFF
Go to sleep command
VCC:
switched off
Communication:
OFF
Table 4-1.
Mode of
Operation
Fail safe
Normal
Silent
Sleep
Mode of Operation
Transceiver
OFF
ON
OFF
OFF
V
CC
3.3V/5V
3.3V/5V
3.3V/5V
0V
RXD
High,
Except after wake-up
LIN depending
High
0V
LIN
Recessive
TXD depending
Recessive
Recessive
5
4957H–AUTO–05/10
京公网安备 11010802033920号
EEWORLD
