MT9080BPR1 datasheet, PDF - EEWORLD Datasheet

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MT9080BPR1: DescriptionTelecom IC, CMOS, PQCC84; CategoryWireless rf/communication Telecom circuit; File Size287KB，31 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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MT9080BPR1 Overview

Telecom IC, CMOS, PQCC84

MT9080BPR1 Parametric

Parameter Name	Attribute value
Maker	Microsemi
Parts packaging code	LCC
Contacts	84
Reach Compliance Code	compliant
JESD-30 code	S-PQCC-J84
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Maximum slew rate	200 mA
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD

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MT9080B

SMX - Switch Matrix Module

Data Sheet

Features

•

16 bit wide data bus I/O

16 bit address bus

Microprocessor Interface

2048 x 16 bit wide memory SRAM

Interfaces with Zarlink’s MT9085B to form larger

switch mitoses

Variable clock and frame rates

Ordering Information

MT9080BP

MT9080BPR

MT9080BP1

MT9080BPR1

84 Pin PLCC

84 Pin PLCC*

*Pb Free Matte Tin

Tubes

Tape & Reel

Tubes

Tape & Reel

March 2006

-40°C to +70°C

Applications

•

Small and medium digital switch matrices

Telephony equipment - PBX, CO equipment,

digital cross connect, digital local loop

Datacom equipment - access concentrators,

Lan/Wan gateways

Description

The MT9080B is a flexible memory module suitable for

use as a basic building block in the construction of

customized digital switching matrices. It can be

configured as either a Data Memory or a Connection

Memory, and is designed to interface with Zarlink’s

MT9085B. Interface to the device is via 16 bit wide

data and address busses. The MT9080B can operate

with variable clock rates up to 16.7 MHz.

D0i/D15i

2048 x 16

Address

MUX

11 Bit

Counter

ENABLE

PRECHARGE

Static

Memory

D0o/

D15o

A0-A15

CRC

Control Interface

Counter

Reset

ODE

CS R/W

DTA

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT9080B

Pin Description

Pin #

Name

Description

Data Sheet

Frame Pulse.

An active low signal that serves as a synchronous clear for the internal 11 bit counter in

all modes except Shift Register mode. The counter is cleared on a rising edge of CK. In the Shift

Chip Select.

Active Low input. Selects the device for microport access in connect memory, data

memory, external and shift register modes. Tying CS high will disable output data drivers (D0-D15o)

in all modes except connect memory and shift register modes.

Data Strobe.

Active low input. Indicates to the SMX that valid data is present on the microport data

bus during a write operation or that the SMX must output data on a read operation.

In Connect Memory modes, a low level applied to this input during a write operation indicates to the

SMX that valid data is present on the microport data bus. During a read operation the low going signal

indicates to the SMX that it must output data on the microport data bus.

In Data Memory and External modes, when DS is high, the output data bus D0o-D15o will be

disabled. The input data bus D0i-D15i is not affected.

The DS input has no effect on the input and output busses in Counter or Shift Register modes.

Read/Write Enable.

Data is written into the device when R/W is low and read from it when it is high.

This control input is disabled in data memory and shift register modes. It should be tied to V

or V

in these modes. In counter and external modes, the state of R/W pin is clocked in with the rising edge

of CK. The actual read or write operation will be implemented on the next rising clock edge.

Data Transfer Acknowledge.

Open drain output which is pulled low to acknowledge completion of

microport data transfer. On a read of the SMX, DTA low indicates that the SMX has put valid data on

the data bus. On a write, DTA low indicates that the SMX has completed latching the data in.

No Connection.

Ground.

No Connection.

Output Data Enable.

Control input which enables the output data bus. Pulling this input low will

place the data bus in a high impedance state. The level on this pin is latched by a rising edge of CK.

The output drivers will be enabled or disabled with the rising edge in the next timeslot (see Fig. 24 for

applicable timing in different modes).

Message Enable.

When tied high the data latched in on the address bus is clocked out on D0o-D15o.

When ME is tied low, the contents of the addressed memory location will be output on the bus. The

level on this pin is latched in with the rising edge of the clock. The actual mode change is

implemented on the rising edge in the next timeslot. Refer to Figures 25 and 26 for more timing

information.

Mode X.

One of three inputs which permit the selection of different operating modes for the device.

Refer to Table 1 for description of various modes.

Mode Y.

See description for pin 37.

Mode Z.

See description for pin 37.

No Connection.

Internal Connection.

Leave open for normal operation.

Ground.

Supply Voltage. +5 V.

No Connection.

R/W

DTA

ODE

41, 42

Zarlink Semiconductor Inc.

MT9080B

Functional Description

Data Sheet

The SMX is a flexible memory module suitable for use in the construction of timeslot interchange circuits used in

PCM voice or data switches. The device can be configured as a data memory or a connection memory.

The SMX has separate 16 bit input and output data busses. A 16 bit address bus and a full microprocessor

interface is also provided.

Data is clocked into and out of the device with the signal applied at the CK (clock) input. Depending on the mode of

operation, the memory locations for the read or write operation can be addressed sequentially by the internal

counter or randomly via the external address bus. A messaging sub-mode, which permits the data latched in on

the address bus to be multiplexed on to the output data bus, is also available (see ME pin description).

The SMX ensures integrity of the stored data by performing a Cyclic Redundancy Check (CRC) on a per frame

basis. When a change in the memory contents is detected from one frame to the next, the Change Detect (CD) pin

is pulled low. The output will be reset to its normal high impedance state when DS input is strobed while CS is low

(i.e., while the device has been selected for microprocessor access). The CD output is not pulled low when the

memory contents have been modified by a processor access to the device.

Modes Of Operation

The SMX can be programmed to operate in one of eight modes as summarized in Table 1. The different modes are

used to realize specific switch implementations. For example, to implement a 1024 channel switch, two SMXs are

required. One is operated in Data Memory mode, while the second is operated in Connect Memory mode. A 2048

channel switch can be realized using three SMXs. Two of the devices are operated, alternatively, in Counter and

External modes, the third serves as the Connection Memory. A detailed description of the implementation is

presented in the Applications section of this data sheet. An outline of the device functionality in each mode is

presented below.

Mode

Name

Data Memory - 1

Data Memory - 2

Connect Memory - 1

Connect Memory - 2

Counter Mode

External Mode

Shift Register Mode

Data Memory - 3

Abbr.

DM-1

DM-2

CM-1

CM-2

CNT

EXT

DM-3

Table 1 - SMX Modes of Operation

Data Memory Mode-1

Data Memory Mode-1 is designed for use in the construction of a 1024 Channel Switch Matrix. Data on the D0-D15

input bus is clocked into the SMX and stored in memory locations addressed by the internal 11 bit counter. Data is

clocked out according to the addresses asserted on the address bus. The pin configuration of the device in this

mode is illustrated in Figure 3.

Zarlink Semiconductor Inc.

MT9080BPR1 Related Products

	MT9080BPR1	MT9080BP1	MT9080BPR
Description	Telecom IC, CMOS, PQCC84	Telecom IC, CMOS, PQCC84	Telecom IC, CMOS, PQCC84
Maker	Microsemi	Microsemi	Microsemi
Parts packaging code	LCC	LCC	LCC
Contacts	84	84	84
Reach Compliance Code	compliant	compliant	unknown
JESD-30 code	S-PQCC-J84	S-PQCC-J84	S-PQCC-J84
Number of terminals	84	84	84
Maximum operating temperature	70 °C	70 °C	70 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ	LDCC84,1.2SQ	LDCC84,1.2SQ
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
power supply	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	200 mA	200 mA	200 mA
Nominal supply voltage	5 V	5 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER
Terminal form	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD

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