IDT7040LA35C datasheet, PDF - EEWORLD Datasheet

IDT7040LA35C: DescriptionDual-Port SRAM, 1KX8, 35ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48; Categorystorage storage; File Size412KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT7040LA35C Overview

Dual-Port SRAM, 1KX8, 35ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
Contacts	48
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	BATTERY BACK-UP
I/O type	COMMON
JESD-30 code	R-CDIP-T48
JESD-609 code	e0
length	60.96 mm
memory density	8192 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Number of functions	1
Number of ports	2
Number of terminals	48
word count	1024 words
character code	1000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP48,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.826 mm
Maximum standby current	0.0015 A
Minimum standby current	2 V
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	15.24 mm

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