W83977AF-A datasheet, PDF - EEWORLD Datasheet

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W83977AF-A: DescriptionWINBOND I/O; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1011KB，182 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W83977AF-A Overview

WINBOND I/O

W83977AF-A Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	PLASTIC, QFP-128
Contacts	128
Reach Compliance Code	_compli
Other features	ON CHIP FDC AND UART
Address bus width	16
boundary scan	NO
Bus compatibility	PC-XT; PC-AT; ISA; PS/2
maximum clock frequency	48 MHz
External data bus width	8
JESD-30 code	R-PQFP-G128
JESD-609 code	e0
length	20 mm
Number of I/O lines	21
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	256
Maximum seat height	3.32 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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WINBOND I/O

W83977F-A/W83977G-A

W83977AF-A/W83977AG-A

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A

Table of Contents-

1. GENERAL DESCRIPTION ................................................................................................................ 1

2. FEATURES ........................................................................................................................................ 2

3. PIN CONFIGURATION...................................................................................................................... 5

4. PIN DESCRIPTION ........................................................................................................................... 6

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.1

Host Interface.......................................................................................................................... 6

Advanced Power Management............................................................................................... 8

Serial Port Interface ................................................................................................................ 9

Infrared Interface................................................................................................................... 10

Multi-Mode Parallel Port........................................................................................................ 11

FDC Interface........................................................................................................................ 15

KBC Interface........................................................................................................................ 16

RTC Interface........................................................................................................................ 16

POWER PINS ....................................................................................................................... 16

W83977F/G and W83977AF/AG FDC .................................................................................. 17

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

AT interface ............................................................................................................................17

FIFO (Data) ............................................................................................................................17

Data Separator .......................................................................................................................18

Write Precompensation ..........................................................................................................18

Perpendicular Recording Mode ..............................................................................................18

FDC Core ...............................................................................................................................19

FDC Commands.....................................................................................................................19

Status Register A (SA Register) (Read base address + 0).....................................................28

Status Register B (SB Register) (Read base address + 1).....................................................30

Digital Output Register (DO Register) (Write base address + 2) ............................................31

Tape Drive Register (TD Register) (Read base address + 3).................................................31

Main Status Register (MS Register) (Read base address + 4)...............................................33

Data Rate Register (DR Register) (Write base address + 4) ..................................................33

FIFO Register (R/W base address + 5) ..................................................................................34

Digital Input Register (DI Register) (Read base address + 7).................................................36

Configuration Control Register (CC Register) (Write base address + 7) ................................38

5. FDC FUNCTIONAL DESCRIPTION................................................................................................ 17

5.2

Register Descriptions ............................................................................................................ 27

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

6. UART PORT .................................................................................................................................... 39

6.1

6.2

Universal Asynchronous Receiver/Transmitter (UART A, UART B) .................................... 39

Register Address................................................................................................................... 39

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

UART Control Register (UCR) (Read/Write) ..........................................................................39

UART Status Register (USR) (Read/Write) ............................................................................41

Handshake Control Register (HCR) (Read/Write) ..................................................................42

Handshake Status Register (HSR) (Read/Write)....................................................................43

UART FIFO Control Register (UFR) (Write only)....................................................................44

-II

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A

6.2.6

6.2.7

6.2.8

6.2.9

Interrupt Status Register (ISR) (Read only) ............................................................................45

Interrupt Control Register (ICR) (Read/Write).........................................................................46

Programmable Baud Generator (BLL/BHL) (Read/Write).......................................................46

User-defined Register (UDR) (Read/Write) ............................................................................47

7. INFRARED (IR) PORT..................................................................................................................... 48

7.1

7.2

IR Register Description ......................................................................................................... 48

Set0-Legacy/Advanced IR Control and Status Registers..................................................... 49

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) .......................49

Set0.Reg1 - Interrupt Control Register (ICR)..........................................................................50

Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) ..........................51

Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): .........................................55

Set0.Reg4 - Handshake Control Register (HCR) ...................................................................55

Set0.Reg5 - IR Status Register (USR) ...................................................................................57

Set0.Reg6 - Reserved ............................................................................................................57

Set0.Reg7 - User Defined Register (UDR/AUDR) ..................................................................57

Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ...............................................................59

Set1.Reg 2~7 .........................................................................................................................59

Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ..................................................60

Reg2 - Advanced IR Control Register 1 (ADCR1) ..................................................................60

Reg3 - Sets Select Register (SSR).........................................................................................61

Reg4 - Advanced IR Control Register 2 (ADCR2) ..................................................................61

Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ........................................................63

Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)............................................................63

Reg0 - Advanced IR ID (AUID)...............................................................................................63

Reg1 - Mapped IR Control Register (MP_UCR) .....................................................................64

Reg2 - Mapped IR FIFO Control Register (MP_UFR) ............................................................64

Reg3 - Sets Select Register (SSR).........................................................................................64

Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH) .............................................................64

Set4.Reg2 - Infrared Mode Select (IR_MSL) ..........................................................................65

Set4.Reg3 - Set Select Register (SSR) ..................................................................................65

Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH) ...................................................65

Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH) ......................................................66

Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) .................66

Set5.Reg2 - Flow Control Mode Operation (FC_MD) .............................................................67

Set5.Reg3 - Sets Select Register (SSR) ................................................................................68

Set5.Reg4 - Infrared Configure Register 1 (IRCFG1).............................................................68

Set5.Reg5 - Frame Status FIFO Register (FS_FO) ...............................................................69

7.3

Set1 - Legacy Baud Rate Divisor Register ........................................................................... 59

7.3.1

7.3.2

7.4

Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)............................................ 59

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.5

Set3 - Version ID and Mapped Control Registers................................................................. 63

7.5.1

7.5.2

7.5.3

7.5.4

7.6

Set4 - TX/RX/Timer counter registers and IR control registers. ........................................... 64

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.7

Set 5 - Flow control and IR control and Frame Status FIFO registers.................................. 66

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

-III -

Publication Release Date: May 2006

Revision 0.60

W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A

7.7.6

Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number

(LST_NU) .............................................................................................................................................69

7.8

Set6 - IR Physical Layer Control Registers .......................................................................... 70

7.8.1

7.8.2

7.8.3

7.8.4

7.8.5

Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)...........................................................70

Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width..............................................................71

Set6.Reg2 - SIR Pulse Width .................................................................................................72

Set6.Reg3 - Set Select Register.............................................................................................72

Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) .................................72

Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) ...................................................73

Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) ...............................................75

Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) .....................................................76

Set7.Reg3 - Sets Select Register (SSR) ................................................................................77

Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) ...............................................77

Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) ...............................................78

Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) ...............................................78

Set7.Reg7 - Infrared Module Control Register (IRM_CR).......................................................79

7.9

Set7 - Remote control and IR module selection registers .................................................... 73

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.9.7

7.9.8

8. PARALLEL PORT ............................................................................................................................ 81

8.1

8.2

Printer Interface Logic ........................................................................................................... 81

Enhanced Parallel Port (EPP)............................................................................................... 82

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

Data Swapper.........................................................................................................................82

Printer Status Buffer ...............................................................................................................83

Printer Control Latch and Printer Control Swapper.................................................................84

EPP Address Port...................................................................................................................84

EPP Data Port 0-3 ..................................................................................................................85

Bit Map of Parallel Port and EPP Registers............................................................................85

EPP Pin Descriptions .............................................................................................................86

EPP Operation .......................................................................................................................86

ECP Register and Mode Definitions .......................................................................................87

Data and ecpAFifo Port ..........................................................................................................88

Device Status Register (DSR) ................................................................................................88

Device Control Register (DCR)...............................................................................................89

cFifo (Parallel Port Data FIFO) Mode = 010 ...........................................................................89

ecpDFifo (ECP Data FIFO) Mode = 011.................................................................................90

tFifo (Test FIFO Mode) Mode = 110 .......................................................................................90

cnfgA (Configuration Register A) Mode = 111 ........................................................................90

cnfgB (Configuration Register B) Mode = 111 ........................................................................90

ecr (Extended Control Register) Mode = all............................................................................91

Bit Map of ECP Port Registers ...............................................................................................92

ECP Pin Descriptions .............................................................................................................93

ECP Operation .......................................................................................................................93

FIFO Operation ......................................................................................................................94

DMA Transfers .......................................................................................................................94

Programmed I/O (NON-DMA) Mode.......................................................................................94

8.3

Extended Capabilities Parallel (ECP) Port............................................................................ 87

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.3.12

8.3.13

8.3.14

8.3.15

8.3.16

-IV

W83977AF-A Related Products

	W83977AF-A	W83977AF-P	W83977AG-A	W83977F-A	W83977F-P	W83977G-A
Description	WINBOND I/O	WINBOND I/O	WINBOND I/O	WINBOND I/O	WINBOND I/O	WINBOND I/O
Is it Rohs certified?	incompatible	incompatible	conform to	incompatible	incompatible	conform to
Parts packaging code	QFP	QFP	QFP	QFP	QFP	QFP
package instruction	PLASTIC, QFP-128	PLASTIC, QFP-128	LEAD FREE, PLASTIC, QFP-128	PLASTIC, QFP-128	PLASTIC, QFP-128	LEAD FREE, PLASTIC, QFP-128
Contacts	128	128	128	128	128	128
Reach Compliance Code	_compli	_compli	unknow	_compli	_compli	unknow
Other features	ON CHIP FDC AND UART	ON CHIP FDC AND UART	ON CHIP FDC AND UART	ON CHIP FDC AND UART	ON CHIP FDC AND UART	ON CHIP FDC AND UART
Address bus width	16	16	16	16	16	16
boundary scan	NO	NO	NO	NO	NO	NO
Bus compatibility	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2	PC-XT; PC-AT; ISA; PS/2
maximum clock frequency	48 MHz	48 MHz	48 MHz	48 MHz	48 MHz	48 MHz
External data bus width	8	8	8	8	8	8
JESD-30 code	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
Number of I/O lines	21	21	21	21	21	21
Number of terminals	128	128	128	128	128	128
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	FQFP	FQFP	FQFP	FQFP	FQFP	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20	QFP128,.67X.93,20	QFP128,.67X.93,20	QFP128,.67X.93,20	QFP128,.67X.93,20	QFP128,.67X.93,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	256	256	256	256	256	256
Maximum seat height	3.32 mm	3.32 mm	3.32 mm	3.32 mm	3.32 mm	3.32 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
JESD-609 code	e0	e0	-	e0	e0	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	-
Maker	-	-	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation

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