MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21267-P/AP
PS21267-P/AP
TRANSFER-MOLD TYPE
TRANSFER-MOLD TYPE
INSULATED TYPE
INSULATED TYPE
PS21267
INTEGRATED POWER FUNCTIONS
600V/30A low-loss CSTBT
TM
inverter bridge for three
phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
•
•
•
•
•
For upper-leg IGBT
S
:Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
For lower-leg IGBT
S
: Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
Input interface : 3, 5V line compatible. (High Active)
UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (Short-pin type : PS21267-P)
Refer Fig. 6 for long-pin type : PS21267-AP.
Dimensions in mm
NOTE
27×2.8(=75.6)
2.8
±0.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16 17 18 19 20 21
TERMINAL CODE
D
Heat sink side
Type name , Lot No.
11.5
±0.5
2-φ4.5
±0.2
13.4
±0.5
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
UP
VP1
VUFB
VUFS
VP
VP1
VVFB
VVFS
WP
VP1
VPC
VWFB
VWFS
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
VN1
VNC
CIN
CFO
FO
UN
VN
WN
P
U
V
W
N
21.4
±0.5
34.9
±0.5
31
±0.5
(11.5)
3.8
±0.2
22
23
24
25
26
10
±0.3
10
±0.3
10
±0.3
67
±0.3
79
±0.5
B
20
±0.3
(8.5)
A
28
±0.5
Irregular solder remains
0.5MAX
C
1
±0.2
1
±0.2
0.7
±0.2
0.7
±0.2
0.8
±0.2
Irregular solder remains
0.5MAX
0.8
±0.2
0.45
±0.2
0.8
±0.2
0.45
±0.2
0.45
±0.2
0.6
±0.5
C0
8
±0.5
12.8
±0.5
.2
C
0.
2
(2.5)
(71)
Heat sink side
OTHERS
TERMINAL 22, 26
DETAIL B
(5 pins t = 0.7)
OTHERS
TERMINAL 1-2, 20-21
DETAIL C
(21 pins t = 0.7)
0.5
±0.2
DETAIL A
(0 ~ 5°)
DETAIL D
Note: All outer lead terminals are with Pb-free solder plating.
Oct. 2005
0.6
±0.5
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21267-P/AP
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBW+
CBW–
CBV+
CBV–
CBU–
CBU+
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system.)
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering
High-side input (PWM)
(3, 5V line) (Note 1, 2)
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
C2
(Note 7)
C1
(Note 6)
DIP-IPM
Inrush current
limiter circuit
P
Drive circuit Drive circuit Drive circuit
AC line input
H-side IGBT
S
(Note 4)
U
V
W
M
AC line output
C
Z
N1
V
NC
N
CIN
L-side IGBT
S
Drive circuit
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment.)
Input signal conditioning
Fo logic
Protection
circuit
Control supply
Under-Voltage
protection
F
O
CFO
Low-side input (PWM)
(3, 5V line) (Note 1, 2) Fault output (5V line)
(Note 3, 5)
(Note 7)
V
NC
V
D
(15V line)
Note1:
2:
3:
4:
5:
6:
7:
The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor.
If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible.
This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor.
The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and V
NC
terminals. (Example : C
FO
=22nF
→
t
FO
=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
To prevent IC
S
from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
I
C
(A)
SC Protection
Trip Level
H-side IGBT
S
U
V
W
L-side IGBT
S
External protection circuit
N1
Shunt Resistor
(Note 1)
A
N
V
NC
CIN
B
Drive circuit
Collector current
waveform
C R
C
Protection circuit
(Note 2)
0
2
t
w
(µs)
Note1:
2:
In the recommended external protection circuit, please select the RC
time constant in the range 1.5~2.0µs.
To prevent erroneous protection operation, the wiring of A, B, C should
be as short as possible.
Oct. 2005
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21267-P/AP
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CC
V
CC(surge)
V
CES
±I
C
±I
CP
P
C
T
j
Parameter
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Condition
Applied between P-N
Applied between P-N
T
C
= 25°C
T
C
= 25°C, less than 1ms
T
C
= 25°C, per 1 chip
(Note 1)
Ratings
450
500
600
30
60
55.5
–20~+125
Unit
V
V
V
A
A
W
°C
Note 1 :
The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T
C
≤
100°C) however, to in-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to T
j(ave)
≤
125°C (@ T
C
≤
100°C).
CONTROL (PROTECTION) PART
Symbol
V
D
V
DB
V
IN
V
FO
I
FO
V
SC
Parameter
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
Condition
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
,
V
WFB
-V
WFS
Applied between U
P
, V
P
, W
P
-V
PC
, U
N
, V
N
,
W
N
-V
NC
Applied between F
O
-V
NC
Sink current at F
O
terminal
Applied between CIN-V
NC
Ratings
20
20
–0.5~V
D
+0.5
–0.5~V
D
+0.5
1
–0.5~V
D
+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Parameter
Self protection supply voltage limit
V
CC(PROT)
(short circuit protection capability)
Module case operation temperature
T
C
T
stg
Storage temperature
V
iso
Isolation voltage
Symbol
Condition
V
D
= 13.5~16.5V, Inverter part
T
j
= 125°C, non-repetitive, less than 2
µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connecting
pins to heat-sink plate
Ratings
400
–20~+100
–40~+125
2500
Unit
V
°C
°C
V
rms
Note 2 :
T
C
measurement point
Control terminals
Heat sink
T
C
T
C
Heat sink boundary
Power terminals
Oct. 2005
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21267-P/AP
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
R
th(j-c)Q
R
th(j-c)F
R
th(c-f)F
Parameter
Junction to case thermal
resistance
(Note 3)
Contact thermal resistance
Condition
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Case to fin (per 1 module) thermal grease applied
Min.
—
—
—
Limits
Typ.
—
—
—
Max.
1.80
3.00
0.067
Unit
°C/W
°C/W
°C/W
Note 3 :
Grease with good thermal conductivity should be applied evenly with a thickness of about +100µm~+200µm on the contact surface
of DIP-IPM and heat-sink.
ELECTRICAL CHARACTERISTICS
(T
j
= 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CE(sat)
V
EC
t
on
t
rr
t
c(on)
t
off
t
c(off)
I
CES
Parameter
Collector-emitter saturation
voltage
FWDi forward voltage
Condition
V
D
= V
DB
= 15V
I
C
= 30A, T
j
= 25°C
V
IN
= 5V
I
C
= 30A, T
j
= 125°C
T
j
= 25°C, –I
C
= 30A, V
IN
= 0V
V
CC
= 300V, V
D
= V
DB
= 15V
I
C
= 30A, T
j
= 125°C, V
IN
= 0
↔
5V
Inductive load (upper-lower arm)
T
j
= 25°C
T
j
= 125°C
Min.
—
—
—
0.65
—
—
—
—
—
—
Limits
Typ.
1.50
1.50
1.50
1.25
0.30
0.30
1.70
0.40
—
—
Max.
2.00
2.00
2.00
1.85
—
0.50
2.40
0.70
1
10
Unit
V
V
µs
µs
µs
µs
µs
mA
Switching times
Collector-emitter cut-off
current
V
CE
= V
CES
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
V
D
= V
DB
= 15V
Total of V
P1
-V
PC
, V
N1
-V
NC
V
IN
= 5V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
D
= V
DB
= 15V Total of V
P1
-V
PC
, V
N1
-V
NC
V
IN
= 0V
V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
V
SC
= 0V, F
O
circuit pull-up to 5V with 10kΩ
V
SC
= 1V, I
FO
= 1mA
T
C
= –20~100°C, V
D
= 15V
(Note 4)
V
IN
= 5V
Trip level
Reset level
T
j
≤
125°C
Trip level
Reset level
C
FO
= 22nF
(Note 5)
Min.
—
—
—
—
4.9
—
0.45
1.0
10.0
10.5
10.3
10.8
1.0
2.1
0.8
Limits
Typ.
—
—
—
—
—
—
—
1.5
—
—
—
—
1.8
2.3
1.4
Max.
7.00
0.55
7.00
0.55
—
0.95
0.52
2.0
12.0
12.5
12.5
13.0
—
2.6
2.1
Unit
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
ms
V
V
I
D
Circuit current
V
FOH
Fault output voltage
V
FOL
Short circuit trip level
V
SC(ref)
Input current
I
IN
UV
DBt
Control supply under-voltage
UV
DBr
protection
UV
Dt
UV
Dr
Fault output pulse width
t
FO
ON threshold voltage
V
th(on)
Applied between U
P
, V
P
, W
P
-V
PC
, U
N
, V
N
, W
N
-V
NC
OFF threshold voltage
V
th(off)
Note 4 :
Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is
less than 2.0 times of the collector current rating.
5 :
Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width t
FO
depends on the capacitance value of C
FO
according to the following approximate equation : C
FO
= 12.2
✕
10
-6
✕
t
FO
[F].
Oct. 2005
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21267-P/AP
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Mounting torque
Weight
Heat-sink flatness
Note 6 :
Mounting screw : M4
Condition
Recommended : 1.18 N·m
(Note 6)
Min.
0.98
—
–50
Limits
Typ.
—
54
—
Max.
1.47
—
100
Unit
N·m
g
µm
Measurement point
+ –
3mm
Heat sink
Place to contact
a heat sink
–
+
Heat sink
RECOMMENDED OPERATION CONDITIONS
Symbol
V
CC
V
D
V
DB
∆V
D
,
∆V
DB
t
dead
f
PWM
I
O
PWIN(on)
Parameter
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Allowable r.m.s. current
Condition
Applied between P-N
Applied between V
P1
-V
PC
, V
N1
-V
NC
Applied between V
UFB
-V
UFS
, V
VFB
-V
VFS
, V
WFB
-V
WFS
For each input signal, T
C
≤
100°C
T
C
≤
100°C, T
j
≤
125°C
V
CC
= 300V, V
D
= V
DB
= 15V,
f
PWM
= 5kHz
P.F = 0.8, sinusoidal PWM
f
PWM
= 15kHz
T
C
≤
100°C, T
j
≤
125°C (Note 7)
(Note 8)
200
≤
V
CC
≤
350V,
Below rated current
13.5
≤
V
D
≤
16.5V,
13.0
≤
V
DB
≤
18.5V,
Between rated current and
1.7 times of rated current
–20°C
≤
T
C
≤
100°C,
N-line wiring inductance less
Between 1.7 times and
than 10nH
(Note 9) 2.0 times of rated current
V
NC
Recommended value
Min.
Typ.
Max.
0
13.5
13.0
–1
2
—
—
—
0.3
1.5
3.0
3.6
300
15.0
15.0
—
—
—
—
—
—
—
—
—
400
16.5
18.5
1
—
20
19.0
Arms
11.6
—
—
—
—
µs
Unit
V
V
V
V/µs
µs
kHz
PWIN(off)
Minimum input pulse width
—
V
–5.0
V
NC
variation
between V
NC
-N (including surge)
5.0
Note 7 :
The Allowable r.m.s. current value depends on the actual application conditions.
8 :
Input signal with ON pulse width less than PWIN(on) might make no response.
9 :
IPM might make no response or response delay to next turn-on pulse if off-pulse width is less than PWIN(off). (Please refer to Fig. 4)
Please refer to Fig. 9 for recommended wiring method too.
Oct. 2005
Analog electronics
京公网安备 11010802033920号
EEWORLD
