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Part Number S3098
Revision NC - Oct 17, 2001
S3098
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low power operation
Silicon Germanium BiCMOS technology
Complies with Telcordia and ITU-T
specifications
Supports G.709 and 10 Gigabit Ethernet rates
Supports OC-192 to OC-192 with Forward
Error Correction (FEC) rates
Integrated phase lock loop
Postamp on serial input
VCO Tunable from 9.953 GHz to 10.709 GHz
155.52 MHz REFCLK input (or equivalent
FEC rate)
16-bit parallel, 622.08 Mbps LVDS data path
(or equivalent FEC rate)
Lock detect indicator
Low jitter CML differential or single-ended serial
interface
Recovered 622.08 MHz clock output
(or equivalent FEC rate)
Accepts Active High or Active Low signal detect
inputs for loss of light (programmable)
Accepts LVCMOS or LVPECL signal detect
inputs
Synthesizes parallel output clock during
loss-of-signal conditions
Power 1.3 W (typ)
Compact 15 mm x 15 mm 148-pin CBGA package
DEVICE SPECIFICATION
SONET/SDH/ATM OC-192 1:16 Low Power Receiver
w
/CDR/Postamp
APPLICATIONS
•
•
•
•
•
•
•
•
•
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3098 low power 1:16 receiver with Clock/Data
Recovery (CDR) and integrated postamp is a fully inte-
grated O C-192 des er ialization/clock and data
recovery device. The S3098 receives an OC-192
scrambled NRZ serial signal and recovers the clock.
This recovered clock is then used to re-time and
demultiplex the data into 16 parallel lines. If a loss-of-
signal condition occurs (or LCKREFN is asserted
Low), the internal Phase Lock Loop (PLL) will lock to
the local 155.52 MHz Reference Clock (REFCLK) (or
equivalent FEC rate) to provide a stable clock for
down-stream purposes. The S3098 has a limiting
postamp on the serial input for small signal gain.
The low jitter LVDS interface guarantees compliance
with the bit error rate requirements of the Telcordia and
ITU-T standards. Figure 1,
System Block Diagram,
shows a typical network application.
Figure 1. System Block Diagram
16
AMCC
GANGES
GANGES II
or HUDSON
AMCC
S3097
TX
AMCC
S3098
RX
AMCC
S3090
TIA
AMCC
OTX
ORX
S3090
TIA
AMCC
S3098
RX
AMCC
S3097
TX
16
16
ORX
16
OTX
AMCC
GANGES
GANGES II
or HUDSON
AMCC Confidential and Proprietary
1
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
CONTENTS
FEATURES.............................................................................................................................................................. 1
APPLICATIONS ...................................................................................................................................................... 1
GENERAL DESCRIPTION ...................................................................................................................................... 1
CONTENTS ............................................................................................................................................................. 2
FIGURES ................................................................................................................................................................. 3
TABLES ................................................................................................................................................................... 3
S3098 OVERVIEW .................................................................................................................................................. 4
Suggested Interface Devices ............................................................................................................................. 4
S3098 PIN DESCRIPTION ...................................................................................................................................... 6
Serial Data In (SERDATIP/N) ............................................................................................................................ 6
Reference Clock (REFCLKP/N) ........................................................................................................................ 6
Loop Filter (CAP1, CAP2) ................................................................................................................................. 6
Lock to Reference (LCKREFN) ......................................................................................................................... 6
Signal Detect (SDLVPECLN/SDLVCMOSN) ..................................................................................................... 6
Reset (RSTB) .................................................................................................................................................... 6
Factory Test (TSTSIG, TESTB) ......................................................................................................................... 6
Parallel Output Clock (POCLKP/N) ................................................................................................................... 7
Parallel Output Data (POUTP/N[15:0]) .............................................................................................................. 7
Lock Detect (LOCKDET) ................................................................................................................................... 7
Recovered 622.08 MHz Clock (RX622MCKP/N) .............................................................................................. 7
S3098 FUNCTIONAL DESCRIPTION ..................................................................................................................... 8
Receiver Description ......................................................................................................................................... 8
Postamp ............................................................................................................................................................ 8
Clock Recovery ................................................................................................................................................. 8
Lock Detect ........................................................................................................................................................ 8
Serial-to-Parallel Converter ............................................................................................................................... 8
Power Sequencing ............................................................................................................................................ 8
ORDERING INFORMATION ................................................................................................................................. 23
2
AMCC Confidential and Proprietary
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
FIGURES
Figure 1. System Block Diagram ............................................................................................................................. 1
Figure 2. Functional Block Diagram ......................................................................................................................... 5
Figure 3. S3098 Pinout (Top View) ........................................................................................................................ 12
Figure 4. Compact 15 mm x 15 mm 148-pin CBGA Package ................................................................................ 13
Figure 5. Parallel Data Output Delay from POCLK ................................................................................................ 19
Figure 6. Differential Voltage Measurement .......................................................................................................... 19
Figure 7. Single-Ended Data Input Voltage Measurement .................................................................................... 20
Figure 8. S3098 LVDS Output to LVDS Input ........................................................................................................ 20
Figure 9. -5.2 V ECL Post Amp to S3098 Input DC Coupled Termination ............................................................. 20
Figure 10. -5.2 V ECL TIA to S3098 DC Coupled Termination .............................................................................. 21
Figure 11. +3.3 V Differential LVPECL Driver to S3098 LVPECL Reference Clock Input, AC Coupled Termination 21
Figure 12. External Loop Filter ............................................................................................................................... 21
Figure 13. Single-Ended Termination Scheme ...................................................................................................... 22
TABLES
Table 1. Reference Frequency ................................................................................................................................ 6
Table 2. SDLVCMOSN Connections when using SDLVPECLN Input ..................................................................... 6
Table 3. SDLVPECLN Connections when using SDLVCMOSN Input ..................................................................... 6
Table 4. Input Pin Description and Assignment ....................................................................................................... 9
Table 5. Output Pin Descriptions and Assignment ................................................................................................ 10
Table 6. Common Pin Descriptions and Assignment ............................................................................................. 11
Table 7. Package Thermals ................................................................................................................................... 13
Table 8. Performance Specifications ..................................................................................................................... 14
Table 9. Absolute Maximum Ratings ..................................................................................................................... 15
Table 10. Recommended Operating Conditions .................................................................................................... 16
Table 11. Internally Biased Differential CML Input DC Characteristics .................................................................. 16
Table 12. LVDS Output Characteristics ................................................................................................................. 17
Table 13. Internally Biased Differential LVPECL Input DC Characteristics (REFCLKP/N) .................................... 17
Table 14. Single-Ended LVPECL Input DC Characteristics (SDLVPECLN) .......................................................... 17
Table 15. LVCMOS Input DC Characteristics ........................................................................................................ 18
Table 16. LVCMOS Output DC Characteristics ..................................................................................................... 18
Table 17. AC Characteristics ................................................................................................................................. 18
Table 18. External Loop Filter Components .......................................................................................................... 19
AMCC Confidential and Proprietary
3
S3098 – SONET/SDH/ATM OC-192 1:16
Low Power Receiver w/CDR/Postamp
S3098 OVERVIEW
The S3098 Clock and Data Recovery Unit (CDR) with
Demultiplexer (DeMUX) implements SONET/SDH
deserialization functions. Figure 2,
Functional Block
Diagram,
shows the basic operation of the chip. This
chip can be used to implement the front end of the
SONET equipment, which consists primarily of the par-
allel transmit interface and the serial receive interface.
The chip includes clock and data recovery, serial-to-par-
allel conversion and system timing. The sequence of
receiver operations of the S3098 is as follows:
1.
2.
3.
4.
Serial input to limiting postamp
Clock and data recovery
Serial-to-parallel conversion
16-bit parallel output
Revision NC - Oct 17, 2001
DEVICE SPECIFICATION
Suggested Interface Devices
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
AMCC
GANGES
(S19202)
GANGES II
(S19202CBI20)
HUDSON
(S19203)
MEKONG
(S19204)
S2509
S3090
S3095
S3097
S3196
OC-192 Mapper
OC-192 Mapper
Framer, Digital Wrapper
OC-192 Pointer Processor
Quad backplane device
10 Gbps TIA
10 Gbps TIA with AGC
OC-192 Transmitter
10 Gbps Limiting Amp
4
AMCC Confidential and Proprietary
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