JANKCAH2N7261 datasheet, PDF - EEWORLD Datasheet

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JANKCAH2N7261: DescriptionPower Field-Effect Transistor, 1-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3; CategoryDiscrete semiconductor The transistor; File Size155KB，15 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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JANKCAH2N7261 Overview

Power Field-Effect Transistor, 1-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, DIE-3

JANKCAH2N7261 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIE-3
Reach Compliance Code	compli
Other features	RADIATION HARDENED
Shell connection	DRAIN
Configuration	SINGLE
Maximum drain current (Abs) (ID)	8 A
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-XUUC-N3
Humidity sensitivity level	1
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	UNCASED CHIP
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	N-CHANNEL AND P-CHANNEL
Maximum power dissipation(Abs)	0.8 W
Certification status	Qualified
Guideline	MIL-19500/657A
surface mount	YES
Terminal form	NO LEAD
Terminal location	UPPER
Maximum time at peak reflow temperature	NOT SPECIFIED
Transistor component materials	SILICON
Base Number Matches	1

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The documentation and process conversion

measures necessary to comply with this revision

shall be completed by 26 April 2011.

INCH-POUND

MIL-PRF-19500/657B

26 January 2011

SUPERSEDING

MIL-PRF-19500/657A

22 February 2000

* PERFORMANCE SPECIFICATION SHEET

SEMICONDUCTOR DEVICE, FIELD EFFECT, RADIATION HARDENED, TRANSISTOR DIE,

N AND P-CHANNEL, SILICON

VARIOUS TYPES JANHC AND JANKC

This specification is approved for use by all Departments

and Agencies of the Department of Defense.

The requirements for acquiring the product described herein shall consist of

this specification sheet and MIL-PRF-19500.

1. SCOPE

1.1 Scope. This specification covers the performance requirements for N and P-channel, enhancement-mode,

MOSFET, radiation hardened, power transistor die. Two levels of product assurance are provided for each device

type as specified in MIL-PRF-19500.

* 1.2 Physical dimensions. See figures 1 through 8 herein.

1.3 Maximum ratings. See the applicable performance specification sheet from table I herein.

2. APPLICABLE DOCUMENTS

* 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This

section does not include documents cited in other sections of this specification or recommended for additional

information or as examples. While every effort has been made to ensure the completeness of this list, document

users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this

specification, whether or not they are listed.

2.2 Government documents.

* 2.2.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a

part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are

those cited in the solicitation or contract.

* DEPARTMENT OF DEFENSE SPECIFICATIONS

MIL-PRF-19500

Semiconductor Devices, General Specification for.

* DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-750

Test Methods for Semiconductor Devices.

* (Copies of these documents are available online at

https://assist.daps.dla.mil/quicksearch/

https://assist.daps.dla.mil/

or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D,

Philadelphia, PA 19111-5094.)

* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,

ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to

Semiconductor@dscc.dla.mil.

Since

contact information can change, you may want to verify the currency of this address information using the

ASSIST Online database at

https://assist.daps.dla.mil/.

AMSC N/A

FSC 5961

MIL-PRF-19500/657B

* 2.3 Order of precedence. Unless otherwise noted herein or in the contract, in the event of a conflict between the

text of this document and the references cited herein, the text of this document takes precedence. Nothing in this

document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained.

3. REQUIREMENTS

3.1 General. The requirements for acquiring the product described herein shall consist of this document and

MIL-PRF-19500.

3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a

manufacturer authorized by the qualifying activity for listing on the applicable Qualified Manufacturer's List (QML)

before contract award (see 4.2 and 6.3).

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as

specified in MIL-PRF-19500.

* 3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in

MIL-PRF-19500, and figures 1 through 8 herein.

3.4.1 Lead finish, material, and thickness. The metallization shall be aluminum for the top and chrome-nickel-

silver for the bottom. The nominal thickness of top metallization shall be 3 µm (4 µm nominal for all 60V die). The

nominal thickness of back metallization shall be 0.55 µm.

3.5 Electrostatic discharge protection. The devices covered by this specification require electrostatic protection.

* 3.5.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation

of static charge. However, the following handling practices are recommended (see 3.5).

Devices should be handled on benches with conductive handling devices.

Ground test equipment, tools, and personnel handling devices.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber, or silk in MOS areas.

Maintain relative humidity above 50 percent if practical.

Care should be exercised during test and troubleshooting to apply not more than maximum rated voltage to

any lead.

Gate must be terminated to source, R

≤

100 kΩ, whenever bias voltage is to be applied drain to source.

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