M1021-13I172.6423 datasheet, PDF

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> M1021-13I172.6423

M1021-13I172.6423: DescriptionSupport Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36; CategoryWireless rf/communication Telecom circuit; File Size311KB，10 Pages; ManufacturerIDT (Integrated Device Technology)

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M1021-13I172.6423 Overview

Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M1021-13I172.6423 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCN,
Contacts	36
Reach Compliance Code	unknown
app	SONET;SDH
JESD-30 code	S-CQCC-N36
JESD-609 code	e0
length	8.99 mm
Number of functions	1
Number of terminals	36
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	3.1 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	8.99 mm

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Integrated

Circuit

Systems, Inc.

Product Data Sheet

M1020/21

VCSO B

ASED

LOCK

PLL

ENERAL

ESCRIPTION

The M1020/21 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for optical network systems

supporting up to 2.5Gb data rates.

It can serve to jitter attenuate a

stratum reference clock or a recovered clock in loop

timing mode. The M1020/21 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

SSIGNMENT

(9 x 9 mm SMT)

MR_SEL3

GND

DIF_REF0

nDIF_REF0

REF_SEL

DIF_REF1

nDIF_REF1

VCC

MR_SEL2

MR_SEL0

MR_SEL1

LOL

NBW

VCC

DNC

M1020

M1021

(Top View)

P_SEL0

P_SEL1

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

GND

EATURES

◆

Integrated SAW delay line; low phase jitter of < 0.5ps

rms, typical (12kHz to 20MHz)

◆

Output frequencies of 62.5 to 175 MHz

(Specify VCSO output frequency at time of order)

◆

LVPECL clock output (CML and LVDS options available)

◆

Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

◆

Loss of Lock (LOL) output pin

◆

Narrow Bandwidth control input (NBW pin)

◆

Hitless Switching (HS) options with or without Phase

Build-out (PBO) to enable SONET (GR-253) / SDH

(G.813) MTIE and TDEV compliance during reselection

◆

Pin-selectable feedback and reference divider ratios

◆

Industrial temperature grade available

◆

Single 3.3V power supply

◆

Small 9 x 9 mm SMT (surface mount) package

Figure 1: Pin Assignment

Example I/O Clock Frequency Combinations

Using

M1020-11-155.5200 or M1021-11-155.5200

Input Reference

Clock (MHz)

(M1020)

(M1021)

GND

OP_IN

nOP_OUT

nVC

OP_OUT

nOP_IN

PLL Ratio

(Pin Selectable)

(M1020)

(M1021)

Output Clock

(MHz)

(Pin Selectable)

19.44 or 38.88

77.76

155.52

622.08

8 or 4

0.25

155.52

77.76

Table 1: Example I/O Clock Frequency Combinations

IMPLIFIED

LOCK

IAGRAM

Loop

Filter

M1020/21

NBW

LOL

MUX

DIF_REF0

nDIF_REF0

DIF_REF1

nDIF_REF1

REF_SEL

MR_SEL3:0

Phase

Detector

R Div

VCSO

M Divider

M/R Divider

LUT

P Divider

(1, 2, or TriState)

TriState

FOUT0

nFOUT0

FOUT1

nFOUT1

P_SEL1:0

P Divider

LUT

Figure 2: Simplified Block Diagram

M1020/21 Datasheet Rev 1.0

M1020/21 VCSO Based Clock PLL

Revised 28Jul2004

●

I n t e g r a t e d C i r c u i t S y s t e m s, I n c .

Networking & Communications

●

w w w. i c s t . c o m

●

tel (508) 852-5400

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