CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V+ = +15V, V
REF
= +10V, V
OUT1
= V
OUT2
= 0V, Unless Otherwise Specified
AD7523
T
A
+25
o
C
T
A
MIN-MAX
MIN
MAX
AD7533
T
A
+25
o
C
MIN
MAX
T
A
MIN-MAX
MIN
MAX
UNITS
PARAMETER
SYSTEM PERFORMANCE
Resolution
Nonlinearity
J
K, T
L
Monotonicity
Gain Error
Nonlinearity Tempco
Gain Error Tempco
Output Leakage Current
(Either Output)
DYNAMIC CHARACTERISTICS
Power Supply Rejection
TEST CONDITIONS
MIN
MAX
8
-10V
≤
V
REF
≤
+10V
V
OUT1
= V
OUT2
= 0V
(Note 1, 2, 5)
-
-
-
-
±0.2
±0.1
±0.05
8
-
-
-
-
±0.2
±0.1
±0.05
10
-
-
-
-
±0.2
±0.1
±0.05
10
-
-
-
-
±0.2
±0.1
±0.05
Bits
% of
FSR
% of
FSR
% of
FSR
Guaranteed
All Digital Inputs High
(Note 2)
-10V
≤
V
REF
≤
+ 10V
(Notes 2, 3)
-
-
-
V
OUT1
= V
OUT2
= 0
-
±1.5
±2
±10
±50
-
-
-
-
±1.8
±2
±10
±200
-
-
-
-
Guaranteed
±1.4
±2
±10
±50
-
-
-
-
±1.8
±2
±10
±200
% of
FSR
ppm of
FSR/
o
C
ppm of
FSR/
o
C
nA
V+ = 14.0V to 15.0V
(Note 2)
To 0.2% of FSR,
R
L
= 100Ω (Note 3)
V
REF
= 20Vpp, 200kHz
Sine Wave, All Digital
Inputs Low (Note 3)
-
±0.02
-
±0.03
-
±0.005
-
±0.008
% of
FSR/%
of
∆V+
ns
LSB
Output Current Settling Time
Feedthrough Error
-
-
150
±1/2
-
-
200
±1
-
-
600
±0.05
-
-
800
±0.1
REFERENCE INPUTS
Input Resistance (Pin 15)
All Digital Inputs High
I
OUT1
at Ground (Note 3)
5
-
-
-
20
-500
5
-
-
-
20
-500
5
-
-
-
20
-300
5
-
-
-
20
-300
kΩ
kΩ
ppm/
ο
C
Temperature Coefficient
8-14
AD7523, AD7533
Electrical Specifications
V+ = +15V, V
REF
= +10V, V
OUT1
= V
OUT2
= 0V, Unless Otherwise Specified
(Continued)
AD7523
T
A
+25
o
C
PARAMETER
ANALOG OUTPUT
Output Capacitance
C
OUT1
C
OUT2
C
OUT1
C
OUT2
DIGITAL INPUTS
Low State Threshold, V
IL
High State Threshold, V
IH
Input Current (Low or High),
I
IL
, I
IH
Input Coding
Input Capacitance
V
IN
= 0V or + 15V
See Tables 1 & 3
(Note 3)
-
-
2,4
-
0.8
-
±1
-
2,4
-
0.8
-
±1
-
2.4
-
0.8
-
±1
-
2.4
-
0.8
-
±1
V
V
µA
All Digital Inputs High
(Note 3)
All Digital Inputs Low
(Note 3)
-
-
-
-
100
30
30
100
-
-
-
-
100
30
30
100
-
-
-
-
100
35
35
100
-
-
-
-
100
35
35
100
pF
pF
pF
pF
TEST CONDITIONS
MIN
MAX
T
A
MIN-MAX
MIN
MAX
AD7533
T
A
+25
o
C
MIN
MAX
T
A
MIN-MAX
MIN
MAX
UNITS
Binary/Offset Binary
4
-
4
-
Binary/Offset Binary
4
-
4
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
I+
(Note 5)
All Digital Inputs High or
Low (Excluding Ladder
Network)
-
+5 to +16
2
-
2.5
-
+5 to +16
2
-
2.5
V
mA
NOTES:
1. Full scale range (FSR) is 10V for unipolar and
±10V
for bipolar modes.
2. Using internal feedback resistor, R
FEEDBACK
.
3. Guaranteed by design or characterization and not production tested.
4. Accuracy not guaranteed unless outputs at ground potential.
5. Accuracy is tested and guaranteed at V+ = +15V, only.
Definition of Terms
Nonlinearity:
Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a percent-
age of full scale range or in (sub)multiples of 1 LSB.
Resolution:
It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2
-N
of the full-scale range, e.g. 2
-N
V
REF
for a unipolar
conversion. Resolution by no means implies linearity.
Settling Time:
Time required for the output of a DAC to
settle to within specified error band around its final value
(e.g. 1/2 LSB) for a given digital input change, i.e. all digital
inputs LOW to HIGH and HIGH to LOW.
Gain Error:
The difference between actual and ideal analog
output values at full-scale range, i.e. all digital inputs at
HIGH state. It is expressed as a percentage of full-scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error:
Error caused by capacitive coupling
from V
REF
to I
OUT1
with all digital inputs LOW.
Output Capacitance:
Capacitance from I
OUT1
, and I
OUT2
terminals to ground.
Output Leakage Current:
Current which appears on I
OUT1
,
terminal when all digital inputs are LOW or on I
OUT2
terminal
when all digital inputs are HIGH.
For further information on the use of this device, see the fol-
lowing Application Notes:
A002
“Principles of Data Acquisition and Conversion”
A018
“Do’s and Don’ts of Applying A/D Converters”, by
Peter Bradshaw and Skip Osgood
A042
“Interpretation of Data Conversion Accuracy Specifi-
cations”
8-15
AD7523, AD7533
Detailed Description
The AD7523 and AD7533 are monolithic multiplying D/A
converters. A highly stable thin film R-2R resistor ladder
network and NMOS SPDT switches form the basis of the
converter circuit, CMOS level shifters permit low power TTL/
CMOS compatible operation. An external voltage or current
reference and an operational amplifier are all that is required
for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the
ladder leg currents between I
OUT1
and I
OUT2
buses which
must be held at ground potential. This configuration main-
tains a constant current in each ladder leg independent of
the input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the out-
puts. Use of high threshold switches reduce offset (leakage)
errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first,
see Figure 1. This configuration results in TTL/CMOS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binarily weighted for an ON resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors and high accurate leg currents.
±10V
+15V
V
REF
MSB
DATA
INPUTS
LSB
14 R
FEEDBACK
4
16
AD7523/ 1 OUT1
AD7533
CR1
OUT2
11
3
2
15
GND
R2
-
6
+
V
OUT
NOTES:
1. R1 and R2 used only if gain adjustment is required.
2. CF1 protects AD7523 and AD7533 against negative transients.
FIGURE 2. UNIPOLAR BINARY OPERATION
TABLE 1. UNlPOLAR BINARY CODE - AD7523
DIGITAL INPUT
MSB LSB
11111111
ANALOG OUTPUT
−
V REF
(
256
)
255
10000001
−
V REF
(
256
)
129
128
−
V REF
(
256
)
10000000
= −
V
REF
2
01111111
V+
1 3
4
6
TO LADDER
−
V REF
(
256
)
127
00000001
−
V REF
(
256
)
1
8
9
00000000
NOTES:
−
V REF
(
256
) =
0
1
0
TTL/
CMOS INPUT
2
5
7
I
OUT2
I
OUT1
1. 1LSB
= (
2
−
8
) (
V REF
) = (
256
) (
V REF
)
Zero Offset Adjustment
1. Connect all digital inputs to GND.
FIGURE 1. CMOS SWITCH
2. Adjust the offset zero adjust trimpot of the output opera-
tional amplifier for 0V
±1mV
(max) at V
OUT
.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor V
OUT
for a -V
REF
(1 - 1/2
8
) reading.
3. To increase V
OUT
, connect a series resistor, R2, (0Ω to
250Ω) in the I
OUT1
amplifier feedback loop.
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the V
REF
terminal.
Typical Applications
Unipolar Binary Operation - AD7523 (8 Bit DAC)
The circuit configuration for operating the AD7523 in unipo-
lar mode is shown in Figure 2. With positive and negative
V
REF
values the circuit is capable of 2-Quadrant multiplica-
tion. The “Digital Input Code/Analog Output Value” table for
unipolar mode is given in Table 1.
8-16
AD7523, AD7533
Unipolar Binary Operation - AD7533 (10 Bit DAC)
The circuit configuration for operating the AD7533 in unipo-
lar mode is shown in Figure 2. With positive and negative
V
REF
values the circuit is capable of 2-Quadrant multiplica-
tion. The “Digital Input Code/Analog Output Value” table for
unipolar mode is given in Table 2.
TABLE 2. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB
1111111111
1000000001
(NOTE 1)
NOMINAL ANALOG OUTPUT
1023
−
V REF
(
1024
)
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor V
OUT
for a -V
REF
(1 - 1/2
10
) reading.
3. To increase V
OUT
, connect a series resistor, R2, (0Ω to
250Ω) in the I
OUT1
amplifier feedback loop.
4. To decrease V
OUT
, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the V
REF
terminal.
Bipolar (Offset Binary) Operation - AD7523
The circuit configuration for operating the AD7523 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage val-
ues, Four-Quadrant multiplication can be realized. The “Digi-
tal Input Code/Analog Output Value” table for bipolar mode is
given in Table 3.)
TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523
DIGITAL INPUT
MSB LSB
11111111
ANALOG OUTPUT
−
V REF
(
1024
)
513
512
−
V REF
(
1024
)
511
−
V REF
(
1024
)
1
−
V REF
(
1024
)
1000000000
0111111111
0000000001
0000000000
NOTES:
= −
V
REF
2
−
V REF
(
1024
) =
0
−
V REF
(
128
)
127
1
0
10000001
10000000
01111111
00000001
00000000
NOTES:
1. 1LSB
−
V REF
(
128
)
0
+V
+V
+V
1. V
OUT
as shown in the Functional Diagram.
2. Nominal Full Scale for the circuit of Figure 2 is given by
1023
FS
= −
V
(
1024
)
REF
3. Nominal LSB magnitude for the circuit of Figure 2 is given by
1
LSB
=
V
(
1024
)
REF
( )
REF 128
1
REF
(
128
)
127
128
( )
REF 128
1
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output opera-
tional amplifier for 0V
±1mV
(max) at V
OUT
.
= (
2
−
7
) (
V REF
) = (
128
) (
V REF
)
A “Logic 1” input at any digital input forces the corresponding
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