PM49FL002T-33JC datasheet, PDF

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PM49FL002T-33JC: DescriptionFlash, 256KX8, 120ns, PQCC32,; Categorystorage storage; File Size523KB，46 Pages; ManufacturerProgrammable Microelectronics Corp

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PM49FL002T-33JC Overview

Flash, 256KX8, 120ns, PQCC32,

PM49FL002T-33JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Programmable Microelectronics Corp
package instruction	QCCJ, LDCC32,.5X.6
Reach Compliance Code	unknown
Maximum access time	120 ns
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
memory density	2097152 bit
Memory IC Type	FLASH
memory width	8
Number of departments/size	64
Number of terminals	32
word count	262144 words
character code	256000
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Department size	4K
Maximum standby current	0.0005 A
Maximum slew rate	0.02 mA
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
switch bit	YES
type	NOR TYPE

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Pm49FL002 / Pm49FL004

2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory

FEATURES

• Single Power Supply Operation

- Low voltage range: 3.0 V - 3.6 V

• Standard Intel Firmware Hub/LPC Interface

- Read compatible to Intel

82802 Firmware Hub

devices

- Conforms to Intel LPC Interface Specification

Revision 1.1

• Memory Configuration

Pm49FL002: 256K x 8 (2 Mbit)

- Pm49FL004: 512K x 8 (4 Mbit)

Firmware HUB (FWH)/Low Pin Count (LPC)

Mode

33 MHz synchronous operation with PCI bus

5-signal communication interface for in-system

read and write operations

Standard SDP Command Set

Data# Polling and Toggle Bit features

each block (FWH mode only)

4 ID pins for multiple Flash chips selection

(FWH mode only)

5 GPI pins for General Purpose Input Register

TBL# pin for hardware write protection to Boot

Block

WP# pin for hardware write protection to whole

memory array except Boot Block

Cost Effective Sector/Block Architecture

Pm49FL002: Sixty-four uniform 4 Kbyte

sectors, or sixteen uniform 16 Kbyte blocks

(sector group)

Pm49FL004: One hundred and twenty-eight

uniform 4 Kbyte sectors, or eight uniform 64

Kbyte blocks (sector group)

Address/Address Multiplexed (A/A Mux)

Mode

- 11-pin multiplexed address and 8-pin data I/O

interface

- Supports fast programming on EPROM

programmers

- Standard SDP Command Set

- Data# Polling and Toggle Bit features

Top Boot Block

Pm49FL002: 16 Kbyte top Boot Block

- Pm49FL004: 64 Kbyte top Boot Block

Automatic Erase and Program Operation

Build-in automatic program verification for

extended product endurance

Typical 25 µs/byte programming time

- Typical 50 ms sector/block/chip erase time

Lower Power Consumption

Typical 2 mA active read current

- Typical 7 mA program/erase current

Two Configurable Interfaces

In-System hardware interface: Auto detection of

Firmware Hub (FWH) or Low Pin Count (LPC)

memory cycle for in-system read and write

operations

- Address/Address-Multiplexed (A/A Mux)

interface for programming on EPROM Pro-

grammers during manufacturing

High Product Endurance

Guarantee 100,000 program/erase cycles per

single sector (preliminary)

- Minimum 20 years data retention

Compatible Pin-out and Packaging

32-pin (8 mm x 14 mm) VSOP

- 32-pin PLCC

- Optional lead-free (Pb-free) package

Hardware Data Protection

Chingis Technology Corporation

P-Flash is registered trademark of Chingis Technology Corporation.

Intel is a registered trademark of Intel Corporation.

Issue Date: April, 2006 Rev:1.8

Pm49FL002 / 004

GENERAL DESCRIPTION

The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These

devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-

system or off-system read, erase and program operations. The 12.0 Volt V

power supply are not required for the

program and erase operations of devices. The devices conform to Intel

Low Pin Count (LPC) Interface specification

revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications.

The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic de-

tect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/

A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both

Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great

flexibility and simplicity for design, procurement, and material inventory.

The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector

group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,

or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature

allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase

operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one

single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-

tion.

The program operation of Pm49FL002/004 is executed by issuing the program command code into command

operation of the devices is executed by issuing the sector, block, or chip erase command code into command

on the array which has not been programmed is not required before an erase operation. The devices offer Data#

Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and

erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.

The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The

Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled

by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The

rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers

(FWH mode only).

The Pm49FL002/004 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices are offered in

32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.

Chingis Technology Corporation

Issue Date: April, 2006 Rev: 1.8

Pm49FL002 / 004

PIN DESCRIPTIONS

S YM B OL

T YP E

In te rfa c e

FW H

LPC

D E S C R IP T IO N

A d d re s s Inp uts: F o r inp uting the m ultip le x a d d re s s e s a nd c o m m a nd s in

P P m o d e . R o w a nd co lum n a d d re s s e s a re la tc he d d uring a re a d o r

w rite c yc le co ntro lle d b y R /C # p in.

R o w /C o lum n S e le c t: To ind ic a te the ro w o r c o lum n a d d re s s in P P

m o d e . W he n this p in g o e s lo w, the ro w a d d re s s is la tc he d . W he n this

p in g o e s hig h, the c o lum n a d d re s s is la tc he d .

D a ta Inp uts/O utp uts : U se d fo r A /A M ux m o d e o nly, to inp ut

co m m a nd /d a ta d uring w rite o p e ra tio n a nd to o utp ut d a ta d uring re a d

o p e ra tio n. The d a ta p ins flo a t to tri-s ta te w he n O E # is d is a b le d .

W rite E na b le : A c tiva te the d e vic e fo r w rite o p e ra tio n. W E # is a c tive lo w.

O utp ut E na b le : C o ntro l the d e vic e 's o utp ut b uffe rs d uring a re a d cycle .

O E # is a c tive lo w.

Inte rfa ce C o nfig ura tio n S e le c t: This p in d e te rm ine s w hic h m o d e is

se le cte d . W he n p ulls hig h, the d e vic e e nte rs into A /A M ux m o d e . W he n

p ulls lo w, F W H /L P C m o d e is s e le c te d . This p in m us t b e s e tup d uring

p o w e r-up o r s yste m re s e t, a nd s ta ys no c ha ng e d uring o p e ra tio n. This

p in is inte rna lly p ulle d d o w n w ith a re s is to r b e tw e e n 2 0 -1 0 0 K

Ω .

R e s e t: To re se t the o p e ra tio n o f the d e vic e a nd re turn to s ta nd b y m o d e .

Initia lize : This is a se co nd re s e t p in fo r in-s ys te m us e . IN IT# o r R S T# p in

p ulls lo w w ill initia te a d e vice re s e t.

F W H /L P C G e ne ra l P urp o se Inp uts : U s e d to s e t the G P I_ R E G fo r

sys te m d e s ig n p urp o s e o nly. The va lue o f G P I_ R E G c a n b e re a d

thro ug h F W H inte rfa c e . The s e p ins s ho uld b e s e t a t d e s ire d s ta te

b e fo re the s ta rt o f the P C I clo c k c yc le fo r re a d o p e ra tio n a nd s ho uld

re m a in no c ha ng e until the e nd o f the re a d c yc le . U nus e d G P I p ins m us t

no t b e flo a te d .

To p B lo ck L o c k : W he n p ulls lo w, it e na b le s the ha rd w a re w rite p ro te c tio n

fo r to p b o o t b lo ck . W he n p ulls hig h, it d is a b le s the ha rd w a re w rite

p ro te c tio n.

W rite P ro te ct: W he n p ulls lo w, it e na b le s the ha rd w a re w rite p ro te c tio n

to the m e m o ry a rra y e xc e p t the to p b o o t b lo c k . W he n p ulls hig h, it

d is a b le s ha rd w a re w rite p ro te c tio n.

F W H A d d re ss a nd D a ta : The m a jo r I/O p ins fo r tra ns m itting d a ta ,

a d d re s se s a nd c o m m a nd c o d e in F W H m o d e .

F W H Inp ut: To ind ica te the s ta rt o f a F W H m e m o ry c yc le o p e ra tio n.

A ls o us e d to a b o rt a F H W m e m o ry c yc le in p ro g re s s .

L P C A d d re ss a nd D a ta : The m a jo r I/O p ins fo r tra ns m itting d a ta ,

a d d re s se s a nd c o m m a nd c o d e in L P C m o d e .

L P C F ra m e : To ind ica te the s ta rt o f a L P C m e m o ry c yc le o p e ra tio n.

A ls o us e d to a b o rt a L P C m e m o ry c yc le in p ro g re s s .

F W H /L P C C lo c k: To p ro vid e a s ync hro no us c lo c k fo r F W H a nd L P C

m o d e o p e ra tio ns.

Id e ntific a tio n Inp uts : The se fo ur p ins a re p a rt o f the m e c ha nis m tha t

a llo w s m ultip le F W H d e vic e s to b e a tta c he d to the s a m e b us . The

stra p p ing o f the s e p ins is us e d to id e ntify the c o m p o ne nt. The b o o t

d e vice m us t ha ve ID [3 :0 ] = 0 0 0 0 b a nd it is re c o m m e nd e d tha t a ll

sub se q ue nt d e vic e s sho uld us e s e q ue ntia l up -c o unt s tra p p ing . The s e

p ins a re inte rna lly p ulle d -d o w n w ith a re s is to r b e tw e e n 2 0 -1 0 0 K

Ω .

D e vic e P o w e r S up p ly

G ro und

N o C o nne ctio n

R e s e rve d : R e se rve d func tio n p ins fo r future us e .

A [1 0 :0 ]

R /C #

I/O [7 :0 ]

WE#

OE #

I/O

R S T#

IN IT#

G P I[4 :0 ]

TB L #

WP#

F W H [3 :0 ]

F W H4

L A D [3 :0 ]

LF RA M E #

C LK

I/O

ID [3 :0 ]

GND

RE S

Note: I = Input, O = Output

Chingis Technology Corporation

Issue Date: April, 2006 Rev: 1.8

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