HD-15531/883
March 1997
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531/883 is a high performance CMOS
device intended to service the requirements of MIL-STD-
1553 and similar Manchester II encoded, time division multi-
plexed serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections oper-
ate independently of each other, except for the master reset
and word length functions. This circuit provides many of the
requirements of MIL-STD-1553. The Encoder produces the
sync pulse and the parity bit as well as the encoding of the
data bits. The Decoder recognizes the sync pulse and identi-
fies it as well as decoding the data bits and checking parity.
The HD-15531/883 also surpasses the requirements of MIL-
STD-1553 by allowing the word length to be programmable
(from 2 to 28 data bits). A frame consists of three bits for
sync followed by the data word (2 to 28 data bits) followed by
one bit of parity, thus, the frame length will vary from 6 to 32
bit periods. This chip also allows selection of either even or
odd parity for the Encoder and Decoder separately.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MIL-STD-1553 over both temperature and
voltage. For high speed applications the 15531B will support
a 2.5 Megabit/sec data rate.
The HD-15531/883 can also be used in many party line digi-
tal data communications applications, such as a local area
network or an environmental control system driven from a
single twisted pair or fiber optic cable throughout a building.
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Support of MIL-STD-1553
• Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec
• Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec
• Variable Frame Length to 32-Bits
• Sync Identification and Lock-In
• Separate Manchester II Encode, Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
-55
o
C to +125
o
C
1.25MBIT/SEC
HD1-15531/883
2.5MBIT/SEC
HD1-15531B/883
PKG. NO.
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2962.1
5-170
HD-15531/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
o
C/W
CERDIP Package . . . . . . . . . . . . . . . . . .
35
9
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . .8ns Max
Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max
Sync. Transition Span (TD2) . . . . . . . . . . . 18 TDC Typical, (Note 1)
Short Data Transition Span (TD4) . . . . . . . . 6 TDC Typical, (Note 1)
Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)
TABLE 1. HD-15531/883, HD-15531B/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
SYMBOL
VIL
VIH
VILC
VIHC
VOL
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
MIN
-
MAX
0.2 VCC
-
GND +0.5
-
0.4
UNITS
V
V
V
V
V
PARAMETER
Input LOW Voltage
Input HIGH Voltage
Input LOW Clock Voltage
Input HIGH Clock Voltage
Output LOW Voltage
TEST CONDITIONS
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
IOL = +1.8mA,
VCC = 4.5V (Note 2)
IOH = -3.0mA,
VCC = 4.5V (Note 2)
VI = VCC or GND,
VCC = 5.5V
VIN = VCC = 5.5V,
Outputs Open
(Note 3)
-55
o
C
≤
T
A
≤
+125
o
C 0.7 VCC
-55
o
C
≤
T
A
≤
+125
o
C
-
-55
o
C
≤
T
A
≤
+125
o
C VCC -0.5
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-
Output HIGH Voltage
VOH
1, 2, 3
2.4
-
V
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
µA
Standby Supply Current
ICCSB
1, 2, 3
-
2
mA
Functional Test
NOTES:
FT
7, 8
-
-
-
1. TDC = Decoder clock period = 1/FDC.
2. Interchanging of force and sense conditions is permitted.
3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH
≥
VCC/2 and VOL
≤
VCC/2.
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
(NOTE 2)
CONDI-TIONS
GROUP A
SUB-
GROUPS
HD-15531/883
TEMPERATURE
MIN
MAX
HD-15531B/883
MIN
MAX
UNITS
PARAMETER
SYMBOL
ENCODER TIMING
Encoder
Clock
Frequency
Send Clock
Frequency
FEC
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
15
-
30
MHz
FESC
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
2.5
-
5.0
MHz
5-173