S29WS128J0PBAI113 datasheet, PDF

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S29WS128J0PBAI113: DescriptionFlash, 8MX16, 55ns, PBGA84, 8 X 11.60 MM, FBGA-84; Categorystorage storage; File Size2MB，97 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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S29WS128J0PBAI113 Overview

Flash, 8MX16, 55ns, PBGA84, 8 X 11.60 MM, FBGA-84

S29WS128J0PBAI113 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	VFBGA, BGA84,10X12,32
Contacts	84
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	55 ns
Other features	SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
startup block	BOTTOM/TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B84
length	11.6 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	16,254
Number of terminals	84
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA84,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	4K,32K
Maximum standby current	0.00005 A
Maximum slew rate	0.054 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	8 mm

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S29WS128J/064J

128/64 Megabit (8/4 M x 16-Bit)

CMOS 1.8 Volt-only Simultaneous Read/Write,

Burst Mode Flash Memory

Data Sheet

Distinctive Characteristics

Architectural Advantages

Single 1.8 volt read, program and erase (1.65 to

1.95 volt)

Manufactured on 0.11 µm process technology

Simultaneous Read/Write operation

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

— Four bank architecture: WS128J: 16Mb/48Mb/48Mb/

16Mb, WS064J: 8Mb/24Mb/24Mb/8Mb

Programable Burst Interface

— 2 Modes of Burst Read Operation

— Linear Burst: 8, 16, and 32 words with wrap-around

— Continuous Sequential Burst

Secured Silicon Sector region

— 128 words accessible through a command sequence,

64words for the Factory Secured Silicon Sector and

64words for the Customer Secured Silicon Sector.

Sector Architecture

4 Kword x 16 boot sectors, eight at the top of the address

range, and eight at the bottom of the address range

—

WS128J:

4 Kword X 16, 32 Kword x 254 sectors

Bank A : 4 Kword x 8, 32 Kword x 31 sectors

Bank B : 32 Kword x 96 sectors

Bank C : 32 Kword x 96 sectors

Bank D : 4 Kword x 8, 32 Kword x 31 sectors

—

WS064J:

4 Kword x 16, 32 Kword x 126 sectors.

Bank A : 4 Kword x 8, 32 Kword x 15 sectors

Bank B : 32 Kword x 48 sectors

Bank C : 32 Kword x 48 sectors

Bank D : 4 Kword x 8, 32 Kword x 15 sectors

WS128J : 84-ball (8 mm x 11.6 mm) FBGA package,

WS064J : 80-ball (7 mm x 9 mm) FBGA package

Cyclling Endurance : 1,000,000 cycles per sector

typical

Data retention : 20-years typical

Hardware Features

Handshaking feature available

— Provides host system with minimum possible latency

by monitoring RDY

Hardware reset input (RESET#)

— Hardware method to reset the device for reading

array data

WP# input

— Write protect (WP#) function allows protection of

four outermost boot sectors, regardless of sector

protect status

Persistent Sector Protection

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

— Sectors can be locked and unlocked in-system at V

level

Password Sector Protection

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

ACC input: Acceleration function reduces

programming time; all sectors locked when ACC =

CMOS compatible inputs, CMOS compatible outputs

Low V

write inhibit

Software Features

Supports Common Flash Memory Interface (CFI)

Software command set compatible with JEDEC

42.4 standards

— Backwards compatible with Am29BDS, Am29BDD,

Am29BL, and MBM29BS families

Data# Polling and toggle bits

— Provides a software method of detecting program

and erase operation completion

Erase Suspend/Resume

— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Performance Characteristics

Read access times at 80/66 MHz

— Synchronous latency of 71/56 ns (at 30 pF)

— Asynchronous random access times of 55/55 ns (at

30 pF)

Power dissipation (typical values, C

= 30 pF)

— Burst Mode Read: 18 mA @ 80Mhz

— Simultaneous Operation: 60 mA @ 80Mhz

— Program/Erase: 15 mA

— Standby mode: 0.2 µA

Publication Number

S29WS-J_00

Revision

Amendment

Issue Date

May 11, 2006

This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient

production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to

the valid combinations offered may occur.

D a t a

S h e e t

General Description

The S29WS128J/064J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write,

Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits each. This

device uses a single V

of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-

volt V

on ACC may be used for faster program performance if desired. The device can also be

programmed in standard EPROM programmers.

At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns at 30 pF.

At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency of 56 ns at 30

pF. The device operates within the wireless temperature range of -25°C to +85°C, and is offered

in Various FBGA packages.

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the

memory space into four banks. The device can improve overall system performance by allowing

a host system to program or erase in one bank, then immediately and simultaneously read from

another bank, with zero latency. This releases the system from waiting for the completion of pro-

gram or erase operations.

The device is divided as shown in the following table:

Quantity

Bank

128Mb

64 Mb

Size

4 Kwords

32 Kwords

4 Kwords

The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output En-

able (OE#) to control asynchronous read and write operations. For burst operations, the device

additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface

with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance

read operations.

The burst read mode feature gives system designers flexibility in the interface to the device. The

user can preset the burst length and wrap through the same memory space, or read the flash

array in continuous mode.

The clock polarity feature provides system designers a choice of active clock edges, either rising

or falling. The active clock edge initiates burst accesses and determines when data will be output.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply

Flash standard.

Commands are written to the command register using standard microprocessor

write timing. Register contents serve as inputs to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally latch addresses and data needed for

the programming and erase operations. Reading data out of the device is similar to reading from

other Flash or EPROM devices.

The

Erase Suspend/Erase Resume

feature enables the user to put erase or program on hold

for any period of time to read data from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon

Sector area (One Time Program area) after an erase suspend, then the user must use the proper

command sequence to enter and exit this region. Program suspend is also offered.

S29WS128J/064J

S29WS-J_00_A6 May 11, 2006

D a t a

S h e e t

Table of Contents

Notice On Data Sheet Designations . . . . . . . . . . . ii

Advance Information .......................................................................................ii

Preliminary ..........................................................................................................ii

Combination .......................................................................................................ii

Full Production (No Designation on Document) ...................................ii

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 46

Reading Array Data ...........................................................................................46

Set Configuration Register Command Sequence ..................................... 47

Figure 4. Synchronous/Asynchronous State Diagram .............. 48

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram of Simultaneous Operation Circuit 7

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8

Special Handling Instructions for FBGA Package ........................................8

Read Mode Setting .........................................................................................48

Programmable Wait State Configuration ...............................................48

Table 14. Programmable Wait State Settings .........................49

Standard wait-state Handshaking Option ...............................................49

Table 15. Wait States for Standard wait-state Handshaking ....49

Read Mode Configuration ...........................................................................50

Table 16. Read Mode Settings ..............................................50

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 12

128 Mb Products based on 110 nm Floating Gate Technology ................13

64 Mb Products based on 110 nm Floating Gate Technology .................13

Burst Active Clock Edge Configuration ..................................................50

RDY Configuration ........................................................................................ 50

Configuration Register ......................................................................................50

Table 17. Configuration Register ..........................................51

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 14

Table 1. Device Bus Operations .......................................... 14

Requirements for Asynchronous ReadOperation (Non-Burst) ........... 14

Requirements for Synchronous (Burst) Read Operation ....................... 14

8-, 16-, and 32-Word Linear Burst with Wrap Around .......................15

Table 2. Burst Address Groups ............................................ 15

Reset Command .................................................................................................. 51

Autoselect Command Sequence .................................................................... 51

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence .................................................................................................................... 52

Program Command Sequence .........................................................................53

Unlock Bypass Command Sequence .........................................................53

Figure 5. Program Operation ............................................... 54

Configuration Register ...................................................................................... 16

Handshaking .......................................................................................................... 16

Simultaneous Read/Write Operations with Zero Latency .................... 16

Writing Commands/Command Sequences ................................................. 16

Accelerated Program Operation ....................................................................17

Autoselect Mode ..................................................................................................17

Table 3. Autoselect Codes (High Voltage Method) ................. 18

Chip Erase Command Sequence ................................................................... 54

Sector Erase Command Sequence ................................................................ 55

Erase Suspend/Erase Resume Commands .................................................. 55

Figure 6. Erase Operation ................................................... 56

Sector/Sector Block Protection and Unprotection .................................. 18

Table 4. S29WS128J/064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 18

Table 5. S29WS064J Boot Sector/Sector Block Addresses for

Protection/Unprotection ..................................................... 21

Advanced Sector Protection/Unprotection . . . . 23

Figure 1. Advanced Sector Protection/Unprotection................. 23

Lock Register ....................................................................................................... 24

Table 6. Lock Register ........................................................ 24

Persistent Protection Bits ................................................................................ 24

Figure 2. PPB Program/Erase Algorithm................................. 26

Password Program Command ....................................................................... 57

Password Verify Command ............................................................................. 57

Password Protection Mode Locking Bit Program Command .............. 57

Persistent Sector Protection Mode Locking Bit Program Command 57

Secured Silicon Sector Protection Bit Program Command .................. 58

PPB Lock Bit Set Command ............................................................................ 58

DPB Write/Erase/Status Command ............................................................. 58

Password Unlock Command .......................................................................... 58

PPB Program Command .................................................................................. 59

All PPB Erase Command .................................................................................. 59

PPB Status Command ....................................................................................... 59

PPB Lock Bit Status Command ...................................................................... 59

Command Definitions .......................................................................................60

Table 18. Command Definitions ..........................................60

Dynamic Protection Bits .................................................................................. 26

Persistent Protection Bit Lock Bit .................................................................27

Password Protection Method .........................................................................27

Figure 3. Lock Register Program Algorithm ............................ 28

Write Operation Status . . . . . . . . . . . . . . . . . . . . 62

DQ7: Data# Polling ........................................................................................... 62

Figure 7. Data# Polling Algorithm ........................................ 63

Advanced Sector Protection Software Examples .................................... 29

Table 7. Sector Protection Schemes ..................................... 29

RDY: Ready .......................................................................................................... 63

DQ6: Toggle Bit I ...............................................................................................64

Figure 8. Toggle Bit Algorithm ............................................. 65

Hardware Data Protection Methods ........................................................... 29

WP# Method .................................................................................................. 29

ACC Method ................................................................................................... 29

Low V

Write Inhibit ................................................................................. 29

Write Pulse “Glitch Protection” ............................................................... 30

Power-Up Write Inhibit ............................................................................... 30

DQ2: Toggle Bit II .............................................................................................. 65

Table 19. DQ6 and DQ2 Indications ......................................66

Reading Toggle Bits DQ6/DQ2 .....................................................................66

DQ5: Exceeded Timing Limits ........................................................................66

DQ3: Sector Erase Timer ................................................................................ 67

Table 20. Write Operation Status .........................................67

Common Flash Memory Interface (CFI) . . . . . . 30

Table 8. CFI Query Identification String ................................ 30

Table 9. System Interface String ......................................... 31

Table 10. Device Geometry Definition .................................. 31

Table 11. Primary Vendor-Specific Extended Query ................ 32

Table 12. WS128J Sector Address Table ............................... 33

Table 13. WS064J Sector Address Table ............................... 41

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 68

Figure 9. Maximum Negative Overshoot Waveform................. 68

Figure 10. Maximum Positive Overshoot Waveform ................ 68

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 69

Commercial (C) Devices ............................................................................. 69

Wireless (W) Devices ..................................................................................69

Supply Voltages ...............................................................................................69

May 11, 2006 S29WS-J_00_A6

S29WS128J/064J

D a t a

S h e e t

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 70

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 11. Test Setup ......................................................... 71

Table 21. Test Specifications ............................................... 71

Key to Switching Waveforms . . . . . . . . . . . . . . . 71

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 71

Figure 12. Input Waveforms and Measurement Levels............. 71

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 72

Power-up ......................................................................................................72

CLK Characterization ........................................................................................72

Figure 13. V

Power-up Diagram ........................................ 72

Figure 14. CLK Characterization ........................................... 72

Figure 26. Synchronous Program Operation Timings: CLK Latched

Addresses ......................................................................... 84

Figure 27. Chip/Sector Erase Command Sequence ................. 85

Figure 28. Accelerated Unlock Bypass Programming Timing..... 86

Figure 29. Data# Polling Timings (During Embedded Algorithm) 86

Figure 30. Toggle Bit Timings (During Embedded Algorithm) ... 87

Figure 31. Synchronous Data Polling Timings/Toggle Bit Timings 87

Figure 32. DQ2 vs. DQ6...................................................... 88

Temporary Sector Unprotect ........................................................................88

Figure 33. Temporary Sector Unprotect Timing Diagram ......... 88

Figure 34. Sector/Sector Block Protect and Unprotect Timing

Diagram ........................................................................... 89

Figure 35. Latency with Boundary Crossing ........................... 89

Figure 36. Latency with Boundary Crossing into Program/Erase Bank

........................................................................................90

Figure 37. Example of Wait States Insertion .......................... 91

Figure 38. Back-to-Back Read/Write Cycle Timings................. 92

Synchronous/Burst Read ...................................................................................73

Figure 15. CLK Synchronous Burst Mode Read (rising active CLK).

....................................................................................... 74

Figure 16. CLK Synchronous Burst Mode Read (Falling Active Clock)

....................................................................................... 75

Figure 17. Synchronous Burst Mode Read.............................. 75

Figure 18. 8-word Linear Burst with Wrap Around................... 76

Figure 19. Linear Burst with RDY Set One Cycle Before Data.... 76

Erase and Programming Performance . . . . . . . . 93

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 94

VBH084 - 84-ball Fine-Pitch Ball Grid Array (FBGA) 8x11.6 mm MCP

Compatible Package (128Mb) .......................................................................... 94

VBR080 - 80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm (64Mb)

................................................................................................................................... 95

Asynchronous Mode Read ...............................................................................77

Figure 20. Asynchronous Mode Read with Latched Addresses... 77

Figure 21. Asynchronous Mode Read..................................... 78

Hardware Reset (RESET#) .............................................................................. 78

Figure 22. Reset Timings..................................................... 79

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 96

Revision A0 (July 22, 2004) ............................................................................. 96

Revision A1 (October 6, 2004) .......................................................................96

Revision A2 (December 10, 2004) .................................................................96

Revision A3 (February 19, 2005) ....................................................................96

Revision A4 (June 24, 2005) ............................................................................96

Revision A5 (March 31, 2006) ......................................................................... 96

Revision A6 (April 28, 2006) .......................................................................... 97

Erase/Program Operations .............................................................................80

Figure 23. Asynchronous Program Operation Timings: AVD#

Latched Addresses ............................................................. 81

Figure 24. Asynchronous Program Operation Timings: WE# Latched

Addresses ......................................................................... 82

Figure 25. Synchronous Program Operation Timings: WE# Latched

Addresses ......................................................................... 83

May 11, 2006 S29WS-J_00_A6

S29WS128J/064J

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