1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
GM71C18163C
GM71CS18163CL
Description
The GM71C(S)18163C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)18163C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)18163C/CL offers
Extended Data out(EDO) Mode as a high speed
access mode. Multiplexed address inputs permit
the GM71C(S)18163C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and standard
400mil 44(50)pin plastic TSOP II. The package
size provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t
RAC
t
CAC
GM71C(S)18163C/CL-5
GM71C(S)18163C/CL-6
GM71C(S)18163C/CL-7
50
60
70
13
15
18
t
RC
84
104
124
t
HPC
20
25
30
Pin Configuration
42 SOJ
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
* Low Power
Active : 1045/935/825mW (MAX)
Standby : 11mW (CMOS level : MAX)
0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control
44(50) TSOP II
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
(Top View)
Rev 0.1 / Apr’01
GM71C18163C
GM71CS18163CL
Pin Description
Pin
A0-A9
A0-A9
I/O0-I/O15
RAS
UCAS, LCAS
Function
Address Inputs
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe
Column Address Strobe
Pin
WE
OE
V
CC
V
SS
NC
Function
Read/Write Enable
Output Enable
Power (+5V)
Ground
No Connection
Ordering Information
Type No.
GM71C(S)18163CJ/CLJ -5
GM71C(S)18163CJ/CLJ -6
GM71C(S)18163CJ/CLJ -7
Access Time
50ns
60ns
70ns
Package
400 Mil
42 Pin
Plastic SOJ
GM71C(S)18163CT/CLT -5
GM71C(S)18163CT/CLT -6
GM71C(S)18163CT/CLT -7
50ns
60ns
70ns
400 Mil
44(50) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
T
A
T
STG
V
IN/OUT
V
CC
I
OUT
P
D
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin Relative to V
SS
Supply voltage Relative to V
SS
Short Circuit Output Current
Power Dissipation
Rating
0 ~
+
70
-55 ~
+
125
-1.0 ~
+
7.0V
-1.0 ~
+
7.0V
50
1.0
Unit
C
C
V
V
mA
W
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Rev 0.1 / Apr’01
GM71C18163C
GM71CS18163CL
Recommended DC Operating Conditions
(T
A
= 0 ~
+
70C)
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
4.5
2.4
-1.0
Typ
5.0
-
-
Max
5.5
6.0
0.8
Unit
V
V
V
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
Truth Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
L
LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
H
L
UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
WE
D
H
H
H
L
L
L
L
L
L
H to L
H to L
H to L
D
D
D
D
H
OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
H
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Open
Operation
Standby
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Word
Word
Word
Word
CBR Refresh
or
Self Refresh
(L-series)
RAS-only
Refresh cycle
Read-modify
-write cycle
Delayed Write
cycle
Early write cycle
Read cycle
Notes
1,3
1,3
1,2,3
1,2,3
1,3
1,3
1,3
1,3
Read cycle
(Output disabled)
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.
t
WCS
>= 0ns Early write cycle
t
WCS
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01
GM71C18163C
GM71CS18163CL
DC Electrical Characteristics
(V
CC
= 5V+/-10%, Vss = 0V, T
A
= 0 ~ 70C)
Symbol
V
OH
V
OL
I
CC1
Parameter
Output Level
Output "H" Level Voltage (I
OUT
= -2mA
)
Output Level
Output "L" Level Voltage (I
OUT
=
2
mA)
Operating Current
Average Power Supply Operating Current
(RAS, UCAS or LCAS Cycling
:
t
RC
=
t
RC
min)
Standby Current (TTL)
Power Supply Standby Current
(RAS, UCAS, LCAS = V
IH
,
D
OUT
=
High-Z)
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
RC
= t
RC
min)
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(t
HPC
= t
HPC
min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, UCAS or LCAS
>=
V
CC
- 0.2V, D
OUT
= High-Z)
CAS-before-RAS Refresh Current
(t
RC
= t
RC
min)
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
Min
2.4
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
V
CC
0.4
190
170
150
2
190
170
150
185
165
145
1
150
190
170
150
500
Unit
V
V
Note
mA
1, 2
I
CC2
mA
I
CC3
mA
2
I
CC4
mA
1, 3
I
CC5
mA
uA
5
I
CC6
mA
I
CC7
I
CC8
I
CC9
I
L(I)
I
L(O)
Battery Back Up Operating Current(Standby with CBR Ref.)
(CBR refresh, t
RC
=125us
,
t
RAS
<=
0.3
us,
D
OUT
=
High-Z, CMOS interface)
Standby Current RAS = V
IH
UCAS, LCAS = V
IL
D
OUT
=
Enable
Self-Refresh Mode Current
(RAS, UCAS or LCAS <=0.2V
,
D
OUT
=
High-Z, CMOS interface)
Input Leakage Current
Any Input (0V
<=
V
IN
<=
6V)
Output Leakage Current
(D
OUT
is Disabled, 0V
<=
V
OUT
<=
6V)
uA
4,5
-
5
mA
1
-
-10
-10
300
10
10
uA
uA
uA
5
Note: 1. I
CC
depends on output load condition when the device is selected.
I
CC
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while UCAS and LCAS = V
IH
.
4. CAS = L (
<=
0.2V) while RAS = L (
<=
0.2V).
5. L-version.
Rev 0.1 / Apr’01
GM71C18163C
GM71CS18163CL
Capacitance
(V
CC
= 5V+/-10%, T
A
= 25C)
Symbol
C
I1
C
I2
C
I/O
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
-
-
-
Max
5
7
7
Unit
pF
pF
pF
Note
1
1
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. LCAS and UCAS = V
IH
to disable D
OUT
.
AC Characteristics
(V
CC
= 5V+/-10%, T
A
= 0 ~
+
70C, Note 1, 2, 18, 19, 20)
Test Conditions
Input rise and fall times : 2 ns
Input levels : V
IL
= 0V, V
IH
= 3V
Input timing reference levels : 0.8V, 2.4V
Output timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + C
L
(100 pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
CAS Precharge Time
RAS Pulse Width
CAS Pulse Width
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
CAS Hold Time
CAS to RAS Precharge Time
OE to D
IN
Delay Time
OE Delay Time from D
IN
CAS Delay Time from D
IN
Transition Time (Rise and Fall)
GM71C(S)18163 GM71C(S)18163 GM71C(S)18163
C/CL-6
C/CL-7
C/CL-5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max
t
RC
t
RP
t
CP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ODD
t
DZO
t
DZC
t
T
84
30
7
-
-
-
104
40
10
-
-
-
124
50
13
-
-
-
50
10,000
7
10,000
0
7
0
7
11
9
10
35
5
13
0
0
2
-
-
-
-
37
25
-
-
-
-
-
-
50
60
10,000
10
10,000
0
10
0
10
14
12
13
40
5
15
0
0
2
-
-
-
-
45
30
-
-
-
-
-
-
50
70
10,000
13
10,000
0
10
0
13
14
12
13
45
5
18
0
0
2
-
-
-
-
52
35
-
-
-
-
-
-
50
21
21
3
4
23
22
5
6
6
7
Rev 0.1 / Apr’01