CAT34TS02
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The CAT34TS02 combines a JC42.4 compliant Temperature Sensor
(TS) with 2−Kb of Serial Presence Detect (SPD) EEPROM.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT pin.
The integrated 2−Kb SPD EEPROM is internally organized as 16
pages of 16 bytes each, for a total of 256 bytes. It features a page write
buffer and supports both the Standard (100 kHz) as well as Fast
(400 kHz) I
2
C protocol.
Write operations to the lower half memory can be inhibited via
software commands. The CAT34TS02 features Permanent, as well as
Reversible Software Write Protection, as defined for DDR3 DIMMs.
Features
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TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
(Top View)
For the location of Pin 1, please consult the
corresponding package drawing.
1
V
CC
EVENT
SCL
SDA
•
•
•
•
•
•
JEDEC JC42.4 Compliant Temperature Sensor
Temperature Range: −20°C to +125°C
DDR3 DIMM Compliant SPD EEPROM
Supply Range: 3.3 V
±
10%
I
2
C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
•
Low Power CMOS Technology
•
2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
•
These Devices are Pb−Free and are RoHS Compliant
V
CC
MARKING DIAGRAM
GTX
ALL
YM
G
TSU
ALL
YM
G
TDFN−8
UDFN−8
GTX, TSU = Specific Device Code
A
= Assembly Location Code
LL
= Assembly Lot Number (Last Two Digits)
Y
= Production Year (Last Digit)
M
= Production Month (1 − 9, O, N, D)
G
= Pb−Free Package
SCL
Pin Name
A
2
, A
1
, A
0
SDA
CAT34TS02
EVENT
A
0
, A
1
, A
2
SDA
SCL
EVENT
V
SS
V
CC
V
SS
DAP
PIN FUNCTIONS
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Open−drain Event Output
Power Supply
Ground
Backside Exposed DAP at V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 12
Publication Order Number:
CAT34TS02/D
CAT34TS02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Voltage on any pin (except A
0
) with respect to Ground (Note 1)
Voltage on pin A
0
with respect to Ground
Rating
−45 to +130
−65 to +150
−0.5 to +6.5
−0.5 to +10.5
Units
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. The A
0
pin can be raised to a HV level for RSWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 2)
T
DR
Parameter
Endurance (EEPROM)
Data Retention (EEPROM)
Min
1,000,000
100
Units
Write Cycles
Years
2. Page Mode, V
CC
= 3.3 V, 25°C
Table 3. TEMPERATURE CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
= −20°C to +125°C, unless otherwise specified)
Parameter
Temperature Reading Error
Class B, JC42.4 compliant
Test Conditions/Comments
+75°C
≤
T
A
≤
+95°C, active range
+40°C
≤
T
A
≤
+125°C, monitor range
−20°C
≤
T
A
≤
+125°C, sensing range
ADC Resolution
Temperature Resolution
Conversion Time
Thermal Resistance (Note 3)
q
JA
Junction−to−Ambient (Still Air)
Max
±1.0
±2.0
±3.0
12
0.0625
100
92
Unit
°C
°C
°C
Bits
°C
ms
°C/W
3. Power Dissipation is defined as P
J
= (T
J
− T
A
)/q
JA
, where T
J
is the junction temperature and T
A
is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
= −20°C to +125°C, unless otherwise specified)
Symbol
I
CC
Parameter
Supply Current
Test Conditions/Comments
TS active, SPD and Bus idle
SPD Write, TS shut−down
I
SHDN
I
LKG
V
IL
V
IH
V
OL1
V
OL2
Standby Current
I/O Pin Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
I
OL
= 3 mA, V
CC
> 2.7 V
I
OL
= 1 mA, V
CC
< 2.7 V
TS shut−down; SPD and Bus idle
Pin at GND or V
CC
−0.5
0.7 x V
CC
Min
Max
500
500
10
2
0.3 x V
CC
V
CC
+ 0.5
0.4
0.2
Unit
mA
mA
mA
mA
V
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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CAT34TS02
Table 5. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
= −20°C to +125°C, unless otherwise specified)
Symbol
C
IN
(Note 4)
I
A
(Note 5)
Parameter
SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
Address Input Current (A0, A1, A2)
Product Rev C
V
IN
< V
IH
V
IN
> V
IH
Conditions
V
IN
= 0 V, f = 1 MHz
Max
8
6
35
2
mA
Units
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively
strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
Table 6. A.C. CHARACTERISTICS
(V
CC
= 3.3 V
±
10%, T
A
= −20°C to +125°C) (Note 6)
Symbol
F
SCL
(Note 7)
t
HIGH
t
LOW
t
TIMEOUT
(Note 7)
t
R
(Note 8)
t
F
(Note 8)
t
SU:DAT
(Note 9)
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
HD:DAT
t
DH
(Note 8)
T
i
t
WR
t
PU
(Note 10)
Clock Frequency
High Period of SCL Clock
Low Period of SCL Clock
SMBus SCL Clock Low Timeout
SDA and SCL Rise Time
SDA and SCL Fall Time
Data Setup Time
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
Input Data Hold Time
Output Data Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power−up Delay to Valid Temperature Recording
100
600
600
600
1300
0
200
900
100
5
100
Parameter
Min
10
600
1300
25
35
300
300
Max
400
Units
kHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
6. Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 23. Bus loading must be such as to allow meeting
the V
IL
, V
OL
as well as the various timing limits.
7. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit.
The time−out count−down is activated in the interval between START and STOP when SCL is low and is reset while SCL is high. The minimum
clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component
is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02 Rev. C,
both the TS and the SPD implement the time−out feature.
8. In a “Wired−OR” system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
− t
DH
− t
SU:DAT
, where t
LOW
and t
DH
are actual values (rather than spec limits). A shorter t
DH
leaves more room for a longer SDA t
R
, allowing for a more capacitive bus
or a larger bus pull−up resistor. At the minimum t
LOW
spec limit of 1300 ns, the maximum t
DH
of 900 ns demands a maximum SDA t
R
of 300 ns.
The CAT34TS02’s maximum t
DH
is <700 ns, thus allowing for an SDA t
R
of up to 500 ns at minimum t
LOW
.
9. The minimum t
SU:DAT
of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a t
SU:DAT
of 0 ns.
10. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
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CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
(V
CC
= 3.3 V, T
A
= −20°C to +125°C, unless otherwise specified.)
300
250
200
I
CC
(mA)
150
100
50
0
−25
I
CC
(mA)
0
25
50
T
AMB
(°C)
75
100
125
300
250
200
150
100
50
0
−25
0
25
50
T
AMB
(°C)
75
100
125
Figure 2. TS Active Current (Rev. B)
(I
2
C−bus and SPD EEPROM Idle)
7
6
5
I
SHDN
(mA)
4
3
2
1
0
−50
−25
0
25
50
T
AMB
(°C)
75
100
125
150
0
−25
I
SHDN
(mA)
3
4
Figure 3. TS Active Current (Rev. C)
(I
2
C−bus and SPD EEPROM Idle)
2
1
0
25
50
T
AMB
(°C)
75
100
125
Figure 4. Standby Current (Rev. B) (I
2
C−bus
and SPD EEPROM Idle, TS Shut−down)
500
500
Figure 5. Standby Current (Rev. C) (I
2
C−bus
and SPD EEPROM Idle, TS Shut−down)
400
I
CC_WR
(mA)
I
CC_WR
(mA)
0
25
50
T
AMB
(°C)
75
100
125
400
300
300
200
200
100
−25
100
−25
0
25
50
T
AMB
(°C)
75
100
125
Figure 6. SPD EEPROM Write Current (Rev. B)
(I
2
C−bus Idle, TS Shut−down)
Figure 7. SPD EEPROM Write Current (Rev. C)
(I
2
C−bus Idle, TS Shut−down)
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CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
(V
CC
= 3.3 V, T
A
= −20°C to +125°C, unless otherwise specified.)
4
3
2
Part # 2
1
DT
(°C)
0
−1
Part # 1
−2
−3
−4
−25
0
25
50
T
AMB
(°C)
75
100
125
−2
−3
−4
−25
0
25
50
T
AMB
(°C)
75
100
125
DT
(°C)
1
0
−1
Part # 1
4
3
2
Part # 2
Figure 8. Temperature Read−Out Error (Rev. B)
Figure 9. Temperature Read−Out Error (Rev. C)
80
70
60
50
40
30
20
−25
80
70
60
50
40
30
20
−25
T
CONV
(ms)
0
25
50
T
AMB
(°C)
75
100
125
T
CONV
(ms)
0
25
50
T
AMB
(°C)
75
100
125
Figure 10. A/D Conversion Time (Rev. B)
5.0
4.5
4.0
t
WR
(ms)
3.5
3.0
2.5
2.0
−25
t
WR
(ms)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
−25
Figure 11. A/D Conversion Time (Rev. C)
0
25
50
T
AMB
(°C)
75
100
125
0
25
50
T
AMB
(°C)
75
100
125
Figure 12. EEPROM Write Time (Rev. B)
Figure 13. EEPROM Write Time (Rev. C)
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