ATMEGA162V-1PC datasheet, PDF - EEWORLD Datasheet

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ATMEGA162V-1PC: DescriptionRISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 1MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，289 Pages; ManufacturerAtmel (Microchip)

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ATMEGA162V-1PC Overview

RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 1MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40

ATMEGA162V-1PC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
core architecture	AVR
Device core	AVR
clock speed	16
Memory	1
flash memory	16
were able	0
Has ADC	NO
Address bus width	16
bit size	8
CPU series	AVR RISC
maximum clock frequency	1 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
length	52.324 mm
Number of I/O lines	35
Number of terminals	40
On-chip program ROM width	16
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/3 V
Certification status	Not Qualified
RAM (bytes)	1024
rom(word)	8192
ROM programmability	FLASH
Maximum seat height	4.826 mm
speed	1 MHz
Maximum supply voltage	3.6 V
Minimum supply voltage	1.8 V
Nominal supply voltage	3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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Features

•

High-performance, Low-power AVR

8-bit Microcontroller

•

Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

Non-volatile Program and Data Memories

– 16K Bytes of In-System Self-programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and

Capture Modes

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended

Standby

I/O and Packages

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

Operating Voltages

– 1.8 - 3.6V for ATmega162V

– 2.4 - 4.0V for ATmega162U

– 2.7 - 5.5V for ATmega162L

– 4.5 - 5.5V for ATmega162

Speed Grades

– 0 - 1 MHz for ATmega162V

– 0 - 8 MHz for ATmega162L/U

– 0 - 16 MHz for ATmega162

•

8-bit

ATmega162

ATmega162V

ATmega162U

ATmega162L

Advance

Information

•

Rev. 2513C–AVR–09/02

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega162 provides the following features: 16K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an

external memory interface, 35 general purpose I/O lines, 32 general purpose working

registers, a JTAG interface for Boundary-scan, On-chip Debugging support and pro-

gramming, four flexible Timer/Counters with compare modes, internal and external

interrupts, two serial programmable USARTs, a programmable Watchdog Timer with

Internal Oscillator, an SPI serial port, and five software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register con-

tents but freezes the Oscillator, disabling all other chip functions until the next interrupt

or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping. In

Standby mode, the crystal/resonator Oscillator is running while the rest of the device is

sleeping. This allows very fast start-up combined with low-power consumption. In

Extended Standby mode, both the main Oscillator and the Asynchronous Timer con-

tinue to run.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer, or

by an On-chip Boot Program running on the AVR core. The Boot Program can use any

interface to download the Application Program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is

a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega162 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

ATmega161 and

ATmega162

Compatibility

The ATmega162 is a highly complex microcontroller where the number of I/O locations

supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-

ward compatibility with the ATmega161, all I/O locations present in ATmega161 have

the same locations in ATmega162. Some additional I/O locations are added in an

Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM

space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD

instructions only, not by using IN and OUT instructions. The relocation of the internal

RAM space may still be a problem for ATmega161 users. Also, the increased number of

Interrupt Vectors might be a problem if the code uses absolute addresses. To solve

these problems, an ATmega161 compatibility mode can be selected by programming

the fuse M161C. In this mode, none of the functions in the Extended I/O space are in

use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec-

tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can

replace the ATmega161 on current Printed Circuit Boards. However, the location of

Fuse bits and the electrical characteristics differs between the two devices.

ATmega162(V/U/L)

2513C–AVR–09/02

ATmega162(V/U/L)

ATmega161 Compatibility

Mode

Programming the M161C will change the following functionality:

•

The extended I/O map will be configured as internal RAM once the M161C Fuse is

programmed.

The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page

54 for details.

The double buffering of the USART Receive Registers is disabled. See “AVR

USART vs. AVR UART – Compatibility” on page 165 for details.

Pin change interrupts are not supported (Contol Registers are located in Extended

I/O).

One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.

•

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers

in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be

affected by the ATmega161 compatibility fuse.

Pin Descriptions

VCC

GND

Port A (PA7..PA0)

Digital supply voltage

Ground

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, they will source current if the internal pull-up resistors are activated. The Port

A pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Port A also serves the functions of various special features of the ATmega162 as listed

on page 70.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega162 as listed

on page 70.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running. If the JTAG interface is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a Reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the

ATmega162 as listed on page 73.

2513C–AVR–09/02

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