256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
Features
DDR2 SDRAM VLP Registered DIMM
MT9HVF3272(P) – 256MB
MT9HVF6472(P) – 512MB
MT9HVF12872(P) – 1GB
For component data sheets, refer to Micron’s Web site:
www.micron.com/products
Features
• 240-pin, registered dual in-line memory module,
very low profile, ATCA form factor
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin RDIMM (ATCA form factor)
Height: 17.9mm (0.70in)
Options
• Parity
• Package
–
240-pin DIMM (lead-free)
• Frequency/CAS latency
1
–
2.5ns @ CL = 5 (DDR2-800)
2
–
2.5ns @ CL = 6 (DDR2-800)
2
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB height
–
17.9mm (0.70in)
Marking
P
Y
-80E
-800
-667
-53E
-40E
Notes: 1. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
2. Not available in 256MB module density.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
Features
Table 2:
Addressing
256MB
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
8K
8K A[12:0]
4 BA[1:0]
1KB
256Mb (32 Meg x 8)
1K A[9:0]
1 S0#
512MB
8K
16K A[13:0]
4 BA[1:0]
1KB
512Mb (64 Meg x 8)
1K A[9:0]
1 S0#
1GB
8K
16K A[13:0]
8 BA[2:0]
1KB
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
Table 3:
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H32M8, 256Mb DDR2 SDRAM
Module
Density
256MB
256MB
256MB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT9HVF3272(P)Y-667__
MT9HVF3272(P)Y-53E__
MT9HVF3272(P)Y-40E__
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
Table 4:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8, 512Mb DDR2 SDRAM
Module
Density
512MB
512MB
512MB
512MB
512MB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT9HVF6472(P)Y-80E__
MT9HVF6472(P)Y-800__
MT9HVF6472(P)Y-667__
MT9HVF6472(P)Y-53E__
MT9HVF6472(P)Y-40E__
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
Table 5:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8, 1Gb DDR2 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT9HVF12872(P)Y-80E__
MT9HVF12872(P)Y-800__
MT9HVF12872(P)Y-667__
MT9HVF12872(P)Y-53E__
MT9HVF12872(P)Y-40E__
Notes:
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9HVF6472Y-667C2.
2. Data sheets for the base device parts can be accessed at www.micron.com/products/ddr2.
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6:
Pin Assignments
240-Pin DDR2 RDIMM Front
Pin Symbol Pin Symbol Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
DD
Q
CKE0
61
62
63
64
65
66
Symbol
A4
V
DD
Q
A2
V
DD
V
SS
V
SS
Pin Symbol
91
92
93
94
95
96
97
98
99
100
101
102
103
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
240-Pin DDR2 RDIMM Back
Pin Symbol Pin Symbol Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0/
DQS9
NC/
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/
DQS10
NC/
DQS10#
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/
DQS11
NC/
DQS11#
V
SS
DQ22
DQ23
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
V
SS
DQ28
DQ29
V
SS
DM3/
DQS12
NC/
DQS12#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/
DQS17
NC/
DQS17#
V
SS
CB6
CB7
V
SS
V
DD
Q
CKE1
V
DD
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
Symbol
V
DD
Q
A3
A1
V
DD
CK0
CK0#
V
DD
A0
V
DD
BA1
V
DD
Q
RAS#
S0#
V
DD
Q
ODT0
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
Symbol
DM5/
DQS14
NC/DQS14#
V
SS
DQ46
DQ47
V
SS
67
V
DD
2
NC/P
AR
_I
N
68
69
V
DD
70
A10
71
BA0
72
V
DD
Q
73
WE#
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
1.
2.
3.
4.
CAS#
V
DD
Q
S1#
ODT1
V
DD
Q
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
104 DQS6#
105
106
107
108
109
110
111
112
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/
DQS15
224 NC/DQS15#
V
SS
225
226
227
228
229
230
231
232
53
V
DD
54 NC/BA2
55
1
NC/
E
RR
_O
UT
56
V
DD
Q
57
58
59
60
A11
A7
V
DD
A5
Notes:
113 DQS7#
114 DQS7
115
V
SS
116
117
118
119
120
DQ58
DQ59
V
SS
SDA
SCL
NC/A13
3
V
DD
V
SS
DQ36
DQ37
V
SS
DM4/
DQS13
4
203 NC/DQS13#
173 NC/A15
V
SS
174 NC/A14
4
204
175 V
DD
Q
205
DQ38
176
177
178
179
180
A12
A9
V
DD
A8
A6
206
207
208
209
210
DQ39
V
SS
DQ44
DQ45
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
Vss
DM7/
DQS16
233 NC/DQS16#
234
V
SS
235
DQ62
236
237
238
239
240
DQ63
V
SS
V
DDSPD
SA0
SA1
Pin 55 is NC for non-parity and E
RR
_O
UT
for parity.
Pin 68 is NC for non-parity and P
AR
_I
N
for parity.
Pin 196 is NC for 512MB or A13 for 1GB, 2GB and parity
Pins 173 and 174 are NC or A15 and A14 for parity
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 7:
Symbol
A[15:0]
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one device bank (A10 LOW,
device bank selected by BA[2/1:0]) or all device banks (A10 HIGH). A[12:0] (256MB) and
A[13:0] (512MB 1GB). A[15:14] are connected for parity
Bank address inputs:
BA[2/1:0] define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA[2/1:0] define which mode register
(MR, EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0]
(256MB, 512MB) and BA[2:0] (1GB).
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to
match that of the DQ and DQS pins. If RDQS is disabled, RDQS[8:0] become DM[8:0] and
RDQS#[8:0] are not used.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the SPD EEPROM address range
on the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize communication to and from
the SPD EEPROM.
Check bits.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out
of the SPD EEPROM on the module on the I
2
C bus.
Parity error output:
Parity error found on the command and address bus.
BA[2:0]
Input
CK0, CK0#
Input
CKE0
DM[8:0]/
DQS[17:9]
Input
Input
ODT0
Input
P
AR
_I
N
RAS#, CAS#, WE#
RESET#
S0#
SA[2:0]
SCL
CB[7:0]
DQ[63:0]
DQS[8:0],
DQS#[8:0]
SDA
E
RR
_O
UT
EVENT#
V
DD
/V
DD
Q
V
DDSPD
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Output
(open drain)
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
Supply
Power supply:
1.8V ±0.1V. The component V
DD
and V
DD
Q are connected to the module
V
DD
.
Supply
SPD EEPROM power supply:
+1.7V to +3.6V.
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, SR): 240-Pin DDR2 SDRAM VLP RDIMM
Pin Assignments and Descriptions
Table 7:
Symbol
V
REF
V
SS
NC
RFU
Pin Descriptions (continued)
Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information
Type
Supply
Supply
–
–
Description
Reference voltage:
V
DD
/2.
Ground.
No connect:
These pins are not connected on the module.
Reserved for future use.
PDF: 09005aef81de9391/Source: 09005aef81de9385
HVF9C32_64_128x72.fm - Rev. D 06/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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