CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
End-to-End Resistance
W option
U option
End-to-End Resistance Tolerance
End-to-End Temperature Coefficient W option
U option
R
W
(Note 12)
C
W
(Note 12)
I
LkgRW
Wiper Resistance
Wiper Capacitance
Leakage on RW Pin
Voltage at pin from GND to V
CC
V
CC
= 3.3V @ +25°C,
wiper current = V
CC
/R
TOTAL
-20
±50
±80
70
25
2
4
TEST CONDITIONS
MIN
TYP
MAX
(Note 14) (Note 3) (Note 14)
10
50
+20
UNIT
k
k
%
ppm/°C
(Note 12)
ppm/°C
(Note 12)
pF
µA
VOLTAGE DIVIDER MODE
(measured at R
W
, unloaded)
INL
(Note 8)
DNL
(Note 7)
ZSerror
(Note 5)
FSerror
(Note 6)
TC
V
(Notes 9, 12)
Integral Non-linearity
Differential Non-linearity
Zero-scale Error
Monotonic over all tap positions
W option
U option
Full-scale Error
W option
U option
Ratiometric Temperature Coefficient DCP register set to 40 hex
-1
-0.5
0
0
-5
-2
1
0.5
-1
-1
±4
1
0.5
5
2
0
0
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
LSB
(Note 4)
ppm/°C
FN6310 Rev 1.00
September 9, 2009
Page 3 of 13
ISL22319
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
PARAMETER
V
CC
Supply Current (volatile
write/read)
V
CC
Supply Current (volatile
write/read, non-volatile read)
I
CC2
V
CC
Supply Current (non-volatile
write/read)
V
CC
Supply Current (non-volatile
write/read)
I
SB
V
CC
Current (standby)
TEST CONDITIONS
10k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
50k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
10k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
50k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
V
CC
= +5.5V, 10k DCP, I
2
C interface in
standby state
V
CC
= +3.6V, 10k DCP, I
2
C interface in
standby state
V
CC
= +5.5V, 50k DCP, I
2
C interface in
standby state
V
CC
= +3.6V, 50k DCP, I
2
C interface in
standby state
I
SD
V
CC
Current (shutdown)
V
CC
= +5.5V @ +85°C, I
2
C interface in
standby state
V
CC
= +5.5V @ +125°C, I
2
C interface in
standby state
V
CC
= +3.6V @ +85°C, I
2
C interface in
standby state
V
CC
= +3.6V @ +125°C, I
2
C interface in
standby state
I
LkgDig
t
DCP
(Note 12)
t
ShdnRec
(Note 12)
Leakage Current, at Pins A0, A1,
SHDN, SDA, and SCL
DCP Wiper Response Time
DCP Recall Time from Shutdown
Mode
Voltage at pin from GND to V
CC
SCL falling edge of last bit of DCP data byte
to wiper new position
From rising edge of SHDN signal to wiper
stored position and RH connection
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
Vpor
V
CC
Ramp
t
D
Power-on Recall Voltage
V
CC
Ramp Rate
Power-up Delay
V
CC
above Vpor, to DCP Initial Value
Register recall completed, and I
2
C Interface
in standby state
Minimum V
CC
at which memory recall occurs
2.0
0.2
3
-1
1.5
1.5
1.5
2.6
MIN
(Note 14)
TYP
(Note 3)
MAX
(Note 14)
1
0.5
3.2
2.7
850
550
160
100
3
5
2
4
1
UNIT
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
µs
µs
V
V/ms
ms
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
t
WC
(Note 13)
Non-volatile Write Cycle Time
Temperature T
+55
°C
1,000,000
50
12
20
Cycles
Years
ms
FN6310 Rev 1.00
September 9, 2009
Page 4 of 13
ISL22319
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 3)
MAX
(Note 14)
UNIT
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
V
OL
Cpin
f
SCL
t
sp
t
AA
t
BUF
A1, A0, SHDN, SDA, and SCL Input
Buffer LOW Voltage
A1, A0, SHDN, SDA, and SCL Input
Buffer HIGH Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V
CC
, until
Valid
SDA exits the 30% to 70% of V
CC
window
Time the Bus Must be Free before the SDA crossing 70% of V
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