24C01A/02A/04A
1K/2K/4K 5.0V I
2
C
™
Serial EEPROMs
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Low power CMOS technology
Hardware write protect
Two wire serial interface bus, I
2
C
™
compatible
5.0V only operation
Self-timed write cycle (including auto-erase)
Page-write buffer
1ms write cycle time for single byte
1,000,000 Erase/Write cycles guaranteed
Data retention >200 years
8-pin DIP/SOIC packages
Available for extended temperature ranges
- Commercial (C):
0˚C to +70˚C
- Industrial (I):
-40˚C to +85˚C
- Automotive (E):
-40˚C to +125˚C
PACKAGE TYPES
DIP
A0
A1
A2
V
SS
8-lead
SOIC
1
2
3
4
24C01A
24C02A
24C04A
8
7
6
5
V
CC
WP*
SCL
SDA
A0
A1
A2
V
SS
1
2
3
4
24C01A
24C02A
24C04A
8
7
6
5
V
CC
WP*
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif-
icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.
This device offers fast (1ms) byte write and
extended (-40
°
C to 125
°
C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.
24C01A
Organization
Write Protect
Page Write
Buffer
128 x 8
None
2 Bytes
24C02A
258 x 8
080-0FF
2 Bytes
24C04A
2 x 256 x 8
100-1FF
8 Bytes
14-lead
SOIC
NC
A0
A1
NC
A2
V
SS
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
V
CC
WP
NC
SCL
SDA
NC
24C01A
24C02A
24C04A
* “TEST” pin in 24C01A
BLOCK DIAGRAM
Vcc
Vss
Data
Buffer
(FIFO)
Data Reg.
SDA
A
d
d
r
e
s
s
Vpp
R/W Amp
Slave Addr.
P
o
i
n A0 to
t
e A7
r
Increment
Memory
Array
SCL
Control
Logic
A8
A0 A1 A2 WP
I
2
C is a trademark of Philips Corporation.
©
1996 Microchip Technology Inc.
DS11183D-page 1
This document was created with FrameMaker 4 0 4
24C01A/02A/04A
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
A0
A0, A1, A2
V
SS
SDA
SCL
TEST
WP
V
CC
PIN FUNCTION TABLE
Function
No Function for 24C04A only, Must
be connected to V
CC
or V
SS
Chip Address Inputs
Ground
Serial Address/Data I/O
Serial Clock
(24C01A only) V
CC
or V
SS
Write Protect Input
+5V Power Supply
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C): Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Automotive (E): Tamb = -40
°
C to +125
°
C
Symbol
Min.
Max.
Units
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
Conditions
V
CC
= +5V (
±
10%)
Parameter
V
CC
detector threshold
V
TH
2.8
4.5
SCL and SDA pins:
High level input voltage
V
IH
V
CC
x 0.7 V
CC
+ 1
Low level input voltage
-0.3
V
CC
x 0.3
V
IL
Low level output voltage
V
OL
0.4
A1 & A2 pins:
High level input voltage
V
IH
V
CC
- 0.5 V
CC
+ 0.5
Low level input voltage
V
IL
-0.3
0.5
—
10
Input leakage current
I
LI
Output leakage current
I
LO
—
10
Pin capacitance
—
7.0
C
IN
,
(all inputs/outputs)
C
OUT
Operating current
I
CC
Write
—
3.5
I
CC
Write
—
4.25
I
OL
= 3.2 mA (SDA only)
I
CC
—
750
µ
A
Read
—
100
µ
A
Standby current
I
CCS
Note: This parameter is periodically sampled and not 100% tested
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
V
IN
/V
OUT
= 0V (Note)
Tamb = +25˚C, f = 1 MHz
F
CLK
= 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = 0˚C to +70˚C
F
CLK
= 100 kHz, program cycle time = 1 ms,
Vcc = 5V, Tamb = (I) and (E)
V
CC
= 5V, Tamb= (C), (I) and (E)
SDA=SCL=V
CC
=5V (no PROGRAM active)
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS11183D-page 2
©
1996 Microchip Technology Inc.
24C01A/02A/04A
TABLE 1-3:
AC CHARACTERISTICS
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:S
TA
T
SU
:S
TA
T
HD
:D
AT
T
SU
:D
AT
T
AA
T
SU
:S
TO
T
BUF
Min.
—
4000
4700
—
—
4000
4700
0
250
300
4700
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max.
100
—
—
1000
300
—
—
—
—
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
ns
ns
Time the bus must be free
before a new transmission
can start
Remarks
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Input filter time constant
(SDA and SCL pins)
Program cycle time
T
I
T
WC
—
—
—
.4
.4N
—
100
1
N
—
ns
ms
ms
cycles
Byte mode
Page mode, N=# of bytes
Endurance
—
1M
25
°
C, Vcc = 5.0V, Block
Mode (Note 2)
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
HD
:
DAT
T
SP
T
AA
T
SU
:
DAT
T
SU
:
STO
T
AA
SDA
OUT
T
HD
:
STA
T
BUF
©
1996 Microchip Technology Inc.
DS11183D-page 3
24C01A/02A/04A
2.0
FUNCTIONAL DESCRIPTION
3.3
Stop Data Transfer (C)
The 24C01A/02A/04A supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24C01A/02A/04A works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.
Up to eight 24C01/24c02s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs. Up
to four 24C04As can be connected to the bus, selected
by A1 and A2 chip address inputs. A0 must be tied to
V
CC
or V
SS
for the 24C04A. Other devices can be con-
nected to the bus but require different device codes
than the 24C01A/02A/04A (refer to section Slave
Address).
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.0
BUS CHARACTERISTICS
3.5
Acknowledge
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24C01A/02A/04A does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS11183D-page 4
©
1996 Microchip Technology Inc.
24C01A/02A/04A
4.0
SLAVE ADDRESS
6.0
PAGE PROGRAM MODE
The chip address inputs A0, A1 and A2 of each 24C01A/
02A/04A must be externally connected to either V
CC
or
ground (V
SS
), assigning to each 24C01A/02A/04A a
unique address. A0 is not used on the 24C04A and
must be connected to either V
CC
or V
SS
. Up to eight
24C01A or 24C02A devices and up to four 24C04A
devices may be connected to the bus. Chip selection is
then accomplished through software by setting the bits
A0, A1 and A2 of the slave address to the corresponding
hard-wired logic levels of the selected 24C01A/02A/04A.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01A/02A/04A, followed by the
chip address bits A0, A1 and A2. In the 24C04A, the
seventh bit of that byte (A0) is used to select the upper
block (addresses 100—1FF) or the lower block
(addresses 000—0FF) of the array.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01A/02A/04A
(Figure 4-1).
The 24C01A/02A/04A monitors the bus for its corre-
sponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
To program the 24C01A/02A/04A, the master sends
addresses and data to the 24C01A/02A/04A which is
the slave (Figure 6-1 and Figure 6-2). This is done by
supplying a START condition followed by the 4-bit
device code, the 3-bit slave address, and the R/W bit
which is defined as a logic LOW for a write. This indi-
cates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to
the master during the ninth clock pulse. When the word
address is received by the 24C01A/02A/04A, it places
it in the lower 8 bits of the address pointer defining
which memory location is to be written. (The A0 bit
transmitted with the slave address is the ninth bit of the
address pointer for the 24C04A). The 24C01A/02A/04A
will generate an acknowledge after every 8-bits
received and store them consecutively in a RAM buffer
until a STOP condition is detected. This STOP condi-
tion initiates the internal programming cycle. The RAM
buffer is 2 bytes for the 24C01A/02A and 8 bytes for the
24C04A. If more than 2 bytes are transmitted by the
master to the 24C01A/02A, the device will not acknowl-
edge the data transfer and the sequence will be
aborted. If more than 8 bytes are transmitted by the
master to the 24C04A, it will roll over and overwrite the
data beginning with the first received byte. This does
not affect erase/write cycles of the EEPROM array and
is accomplished as a result of only allowing the address
registers bottom 3 bits to increment while the upper 5
bits remain unchanged.
If the master generates a STOP condition after trans-
mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received data bytes in the page
buffer will be written in a serial manner.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8 for
24C04A, 2 for 24C01A/02A).
FIGURE 4-1:
START
SLAVE ADDRESS
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
5.0
BYTE PROGRAM MODE
In this mode, the master sends addresses and one data
byte to the 24C01A/02A/04A.
Following the START signal from the master, the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C01A/02A/
04A that a byte with a word address will follow after it
has generated an acknowledge bit. Therefore the next
byte transmitted by the master is the word address and
will be written into the address pointer of the 24C01A/
02A/04A. After receiving the acknowledge of the
24C01A/02A/04A, the master device transmits the data
word to be written into the addressed memory location.
The 24C01A/02A/04A acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 24C01A/02A/04A
(Figure 6-1).
©
1996 Microchip Technology Inc.
DS11183D-page 5
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