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M2V56S20AKT-7UL

Description
Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO64, STSOP2-64
Categorystorage    storage   
File Size420KB,51 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
Download Datasheet Parametric View All

M2V56S20AKT-7UL Overview

Synchronous DRAM, 64MX4, 6ns, CMOS, PDSO64, STSOP2-64

M2V56S20AKT-7UL Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeTSOP2
package instructionTSOP, TSSOP64,.42,16
Contacts64
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G64
JESD-609 codee0
length13.1 mm
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals64
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSSOP64,.42,16
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.001 A
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width9.05 mm
MITSUBISHI LSIs
SDRAM (Rev.1.31)
Single Data Rate
Apr. '02
M2V56S20/ 30/ 40 ATP
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
Contents are subject to change without notice.
DESCRIPTION
M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
and are suitable for main memory or graphic memory in computer systems.
FEATURES
Max. Frequency Max. Frequency
@CL2
@CL3
M2V56S20/30/40ATP/KT-5/-5L/-5UL
M2V56S20/30/40ATP/KT-6/-6L/-6UL
M2V56S20/30/40ATP/KT-7/-7L/-7UL
133MHz
100MHz
100MHz
133MHz
133MHz
100MHz
Standard
PC133 (CL2)
PC133 (CL3)
PC100 (CL2)
Note: The –5L/-6L/-7L is Self-refresh low power.
The –5LU/-6UL/-7UL is Self-refresh ultra low power.
- Single 3.3v + 0.3V power supply
- Max. Clock frequency -5:PC133<2-2-2> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- Both 54-pin TSOP Package and 64-pin Small TSOP Package
M2V56S*0ATP: 0.8mm lead pitch 54-pin TSOP Package
M2V56S*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package (sTSOP)
- Low Power for the Self Refresh Current ICC6 : 2.0mA (–5L,-6L,-7L)
- Ultra Low Power for the Self Refresh Current ICC6 : 1.0mA (–5UL,-6UL,-7UL)
MITSUBISHI ELECTRIC
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