71V016SA20Y8 datasheet, PDF - EEWORLD Datasheet

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71V016SA20Y8: DescriptionStandard SRAM, 64KX16, 20ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44; Categorystorage storage; File Size101KB，9 Pages; ManufacturerIDT (Integrated Device Technology)

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71V016SA20Y8 Overview

Standard SRAM, 64KX16, 20ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

71V016SA20Y8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOJ
package instruction	0.400 INCH, PLASTIC, SOJ-44
Contacts	44
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	R-PDSO-J44
JESD-609 code	e0
length	28.575 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Encapsulate equivalent code	SOJ44,.44
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	3.683 mm
Maximum standby current	0.01 A
Minimum standby current	3.15 V
Maximum slew rate	0.12 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm

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3.3V CMOS Static RAM

1 Meg (64K x 16-Bit)

Features

IDT71V016SA

Description

The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized

as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability

CMOS technology. This state-of-the-art technology, combined with inno-

vative circuit design techniques, provides a cost-effective solution for high-

speed memory needs.

The IDT71V016 has an output enable pin which operates as fast

as 5ns, with address access times as fast as 10ns. All bidirectional

inputs and outputs of the IDT71V016 are LVTTL-compatible and operation

is from a single 3.3V supply. Fully static asynchronous circuitry is used,

requiring no clocks or refresh for operation.

The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic

SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.

64K x 16 advanced high-speed CMOS Static RAM

Equal access and cycle times

— Commercial: 10/12/15/20ns

— Industrial: 12/15/20ns

One Chip Select plus one Output Enable pin

Bidirectional data inputs and outputs directly

LVTTL-compatible

Low power consumption via chip deselect

Upper and Lower Byte Enable Pins

Single 3.3V power supply

Available in 44-pin Plastic SOJ, 44-pin TSOP, and

48-Ball Plastic FBGA packages

Functional Block Diagram

Output

Enable

Buffer

– A

Address

Buffers

Row / Column

Decoders

I/O

Chip

Enable

Buffer

Sense

Amps

and

Write

Drivers

Low

Byte

I/O

Buffer

High

Byte

I/O

Buffer

I/O

Write

Enable

Buffer

64K x 16

Memory

Array

I/O

BHE

Byte

Enable

Buffers

BLE

3834 drw 01

JUNE 2002

DSC-3834/06

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