M27V201
2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM
NOT FOR NEW DESIGN
s
s
M27V201 is replaced by the M27W201
3V to 3.6V LOW VOLTAGE in READ
OPERATION
ACCESS TIME: 120ns
LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
1
32
s
s
32
1
s
s
s
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIME: 100µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
FDIP32W (F)
PDIP32 (B)
O
DESCRIPTION
The M27V201 is a low voltage 2 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organised as 262,144 by 8
bits.
The M27V201 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
Figure 1. Logic Diagram
et
l
o
PLCC32 (K)
P
e
od
r
s)
t(
uc
TSOP32 (N)
8 x 20 mm
VCC
VPP
18
A0-A17
8
Q0-Q7
P
E
G
M27V201
VSS
AI00693B
July 2000
This is information on a product still in production but not recommended for new designs.
1/15
M27V201
Figure 2A. DIP Connections
Figure 2B. LCC Connections
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
32
1
31
2
30
3
29
4
28
5
27
6
26
7
25
8
M27V201
24
9
23
10
22
11
21
12
20
13
19
14
18
15
17
16
AI01901
VCC
P
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
A12
A15
A16
VPP
VCC
P
A17
1 32
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
A9
A11
G
A10
E
Q7
9
M27V201
25
17
Q1
Q2
Figure 2C. TSOP Connections
Table 1. Signal Names
O
so
b
A11
A9
A8
A13
A14
A17
P
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
32
te
le
16
8
9
M27V201
(Normal)
r
P
uc
od
25
24
s)
t(
17
AI01154B
G
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
bs
-O
E
G
P
V
PP
V
CC
V
SS
A0-A17
Q0-Q7
et
l
o
P
e
od
r
s)
t(
uc
AI00694
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program
Program Supply
Supply Voltage
Ground
2/15
VSS
Q3
Q4
Q5
Q6
M27V201
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
E
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
G
V
IL
V
IH
V
IH
V
IL
X
X
P
X
X
A9
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
O
so
b
te
le
r
P
A0
uc
od
Q7
0
0
s)
t(
Q6
0
1
bs
-O
Q4
0
0
1
1
V
IL
Pulse
V
IH
X
X
et
l
o
P
e
X
X
X
X
X
X
V
ID
od
r
V
PP
s)
t(
uc
Hi-Z
Q7-Q0
V
CC
or V
SS
V
CC
or V
SS
V
PP
V
PP
V
PP
V
CC
or V
SS
V
CC
Data Out
Data In
Data Out
Hi-Z
Hi-Z
Codes
V
IL
V
IH
Q5
Q3
0
0
Q2
0
0
Q1
0
0
Q0
0
1
Hex Data
20h
61h
V
IL
V
IH
3/15
M27V201
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Note: 1. Sampled only, not 100% tested.
O
DEVICE OPERATION
The operating modes of the M27V201 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27V201 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
Test Condition
V
IN
= 0V
et
l
o
P
e
od
r
s)
t(
uc
OUT
AI01823B
Min
Max
6
12
Unit
pF
pF
V
OUT
= 0V
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27V201 has a standby mode which reduces
the active current from 15mA to 20µA with low volt-
age operation V
CC
≤
3.6V, see Read Mode DC
Characteristics table for details.The M27V201 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
4/15
M27V201
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C or –40 to 85°C; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Output High Voltage CMOS
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –400µA
I
OH
= –100µA
2.4
V
CC
–0.7V
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
≤
3.6V
E = V
IH
E > V
CC
– 0.2V, V
CC
≤
3.6V
V
PP
= V
CC
–0.3
2
Min
Max
±10
±10
15
1
20
10
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85°; V
CC
= 3.3V ± 10%; V
PP
= V
CC
)
Symbol
Alt
Parameter
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
O
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
so
b
te
le
r
P
uc
od
s)
t(
bs
-O
Test Condition
et
l
o
P
e
-120
od
r
Min
s)
t(
uc
V
V
Unit
M27V201
-150
Max
150
150
60
0
0
0
50
50
ns
ns
ns
ns
ns
ns
Min
Max
120
120
50
E = V
IL
, G = V
IL
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
, G = V
IL
0
0
0
40
40
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
5/15
DSP and ARM Processors
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