GS8644ZV18B-250T datasheet, PDF

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GS8644ZV18B-250T: DescriptionZBT SRAM, 4MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FBGA-119; Categorystorage storage; File Size1MB，37 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8644ZV18B-250T Overview

ZBT SRAM, 4MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, FBGA-119

GS8644ZV18B-250T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	6.5 ns
Other features	PIPELINED OR FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	75497472 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.99 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.6 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)

119-, 165-, & 209-Pin BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V +10%/–10% core power supply and I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb

devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-bump BGA package

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–133MHz

1.8 V V

1.8 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8644ZV18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8644ZV18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump, 165-bump or 209-bump BGA package.

Functional Description

The GS8644ZV18/36/72 is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Parameter Synopsis

KQ(x18/x36)

KQ(x72)

tCycle

Curr

(x18)

Curr

(x36)

Curr

(x72)

tCycle

Curr

(x18)

Curr

(x36)

Curr

(x72)

-250 -225 -200

2.3 2.5 2.7

2.6 2.7 2.8

4.0 4.4 5.0

385

450

540

6.5

265

290

345

-166

2.9

6.0

-150

3.3

6.7

-133 Unit

3.5 ns

7.5 ns

Pipeline

3-1-1-1

360 335 305 295 265 mA

415 385 345 325 295 mA

505 460 405 385 345 mA

6.5

8.0

8.5

Flow

Through

2-1-1-1

265 265 255 240 225 mA

290 290 280 265 245 mA

345 345 335 315 300 mA

Rev: 1.03 11/2004

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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