J-Type
Voltage Controlled Crystal Oscillator
Product is compliant to RoHS directive
and fully compatible with lead free assembly
Features
•
Output Frequencies from 1.024 MHz to 170.000 MHz
•
+3.3 or +5.0 volt options
•
Small 14mm x 9mm J-type Package
•
CMOS or PECL Outputs
•
Low phase noise and custom options
•
0/70° C or –40/85° C operating temperature
•
Tri-State output (CMOS) Enable/Disable (PECL)
Applications
•
Clock Smoothing
The J-type Voltage Controlled Crystal Oscillator
•
Frequency Translation
•
SONET, SDH, ATM, DSLAM, ADM
Description
The J-type voltage controlled crystal oscillator
expands VI’s advanced VCXO performance
capabilities while adhering to a package footprint
compatible with the industry-common J-lead package.
The J-type VCXO is a quartz stabilized square wave
generator with either a CMOS output for driving
CMOS/TTL loads or a PECL output. The device is
packaged in a 6 pin J-lead ceramic package and is
hermetically sealed with a grounded conductive lid.
The first section of this data sheet covers the
performance/packaging/tape and reel/ordering
information for the CMOS version and then the
information for the PECL option follows.
Table of Contents
Page 2- 6
-- CMOS
Page 7- 11
-- PECL
Vectron International 267 Lowell Rd. Hudson, NH 03051
Tel:1-88-VECTRON-1
e-mail:
vectron@vectron.com
J-Type Voltage Controlled Crystal Oscillator
Table 1. Pin Out Information for the CMOS output Option
Pin
1
2
3
4
5
6
Symbol
V
C
Tri-State
1
GND
Output
CMOS/TTL
select
1,2
V
CC
Function
VCXO Control Voltage
TTL logic low disables output.
TTL logic high, or no connect, enables output.
Case and Electrical Ground
VCXO Output
TTL logic low optimizes symmetry for CMOS.
TTL logic high, or NC, optimizes symmetry for TTL
Power Supply Voltage (5.0 V or 3.3 V
±10%)
6
5
4
TOP VIEW
1
2
3
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.
2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin
for frequencies < 12MHz.
Table 2. Electrical Performance @ 25°C for the CMOS output option
Parameter
Supply Voltage , +5 volt option
+3.3 volt option
Supply Current
Center Frequency,
see ordering information
Operating Temperature,
see ordering info
Absolute Pull Range over the operating
temperature range, aging and power supply
Vc= 0.5 to 4.5 or 0.3 to 3.0 V
see ordering information for options
Gain Transfer
(Frequency vs. Control Voltage)
Output Level High
2
Output Level Low
2
Output Rise/Fall Time
2
Duty Cycle
3
,
see ordering info
Input Leakage
Control Voltage Modulation Bandwidth
RMS Jitter, 77.760MHz
RMS Jitter, 77.760MHz, 12kHz to 20MHz
Maximum Control Voltage
Maximum Supply Voltage
Storage Temperature
Soldering Temp./Time
1
Symbol
F
N
T
OP
APR
Minimum
Typical Maximum
4.5
5.0
5.5
3.0
3.3
3.6
10mA + 0.25mA per MHz, typical
1.024
77.760
0/70, -40/85
±50
to
±100
Units
V
V
MHz
°C
ppm
K
V
V
OH
V
OL
t
R/
t
F
SYM
I
L
BW
0.8*Vcc
Positive
-
-
45/55 or 40/60
-
10
3
<0.5
±1
-
V
V
ns
%
uA
kHz
ps
ps
V
°C
°C/s
0.1*Vcc
5
0
T
S
T
LS
-55
-
-
-
V
DD
7
125
240/10
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended
.
2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.
3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3
volt operation)
T
R
80
%
T
F
I
DD
6
V
DD
50%
20
%
On Time
Period
2
5
3
650
Ohm
+
-
.
1µF
.01µF
I
C
V
C
1
+
-
4
15pF
1.8k
Ohm
Figure 1. Output Waveform
Figure 2. Output Test Conditions (25±5°C)
for 5 volt devices, 15pF cap only for 3.3V.
Tel:1-88-VECTRON-1
2
e-mail vectron@vectron.com
Vectron International 267 Lowell Rd. Hudson, NH 03051
J-Type Voltage Controlled Crystal Oscillator
Qualification Conformance
The CMOS J-type family has undergone the following Mil-Std qualification:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2015
Handling Precautions
Although ESD protection circuitry has been designed into the the J-type, proper precautions should be
taken when handling and mounting. VI employs a human body model and a charged-device model
(CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on
the circuit parameters used to define the model. Although no industry wide standard has been adopted
for the CDM, a standard HBM of resistance = 1.5Kohms and capacitance = 100pF is widely used and
therefore can be used for comparison purposes.
Table 4. ESD Ratings
Model
Human Body Model (HBM)
Charged Device Model (CDM)
Minimum
1500 V
1500 V
Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
PreHeat Time
Ramp Up
Time Above 217
o
C
Time To Peak Temperature
Time At 260
o
C
Ramp Down
Symbol
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
260
Value
60 sec Min, 180 sec Max
3
o
C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6
o
C/sec Max
t
L
R
UP
t
P
R
DN
Temperature (DegC)
217
200
150
t
S
t
AMB-P
25
Time (sec)
Vectron International 267 Lowell Rd. Hudson, NH 03051
Tel:1-88-VECTRON-1
3
e-mail vectron@vectron.com
J-Type Voltage Controlled Crystal Oscillator
Figure 4. Outline Diagram
Dimensions are in
inches and (millimeters)
0.118
(3.00)
0.200
(5.08)
0.030
(0.077)
0.100
(2.54)
0.346
(8.80)
Figure 5. Suggested Pad Layout
Vectron International 267 Lowell Rd. Hudson, NH 03051
Tel:1-88-VECTRON-1
4
e-mail vectron@vectron.com
J-Type Voltage Controlled Crystal Oscillator
J
C
B
A
E
Bottom Holes for TRU
and VCO Products Only
G
D
F
I
L
H
K
Figure 6. Tape Reel Drawing for CMOS and PECL output option
Table 5. Tape and Reel Dimensions (mm)
Tape Dimensions
Product
A
B
J-Type
24
11.5
C
1.5
D
4
E
12
Reel Dimensions
F
G
H
1.78
21
13
I
100
J
5
K
25
L
330
# Per
Reel
200
Table 6. Ordering Information for the CMOS output version (add frequency)
Package
Supply
Voltage
(V)
C
5V±10%
U
VCXO
Type
VCXO
±10%
linear
VCXO
APR
(ppm)
G
±50
±80
±100
Operating
Temp.
(
°C
)
C
0/70
Output/ Duty
Cycle
Min/Max
A
TTL/
CMOS
45/55%
1
CMOS
45/55%
2
CMOS
40/60%
3
T
Tri-State
Specials
J
6 pin
Ceramic
SOJ
Tri State
on pin 2
N
Standard
D
3.3±10%
L
N
L
-40/ 85
J
H
1.
2.
3.
K
Output is CMOS and symmetry is tested at TTL and CMOS thresholds.
Output is CMOS and symmetry is tested at CMOS threshold. This option is used for 3.3 V operation.
Output is CMOS and symmetry is tested at CMOS thresholds. This option is required for 3.3V, frequencies
>51.840MHz.
4.
Note: Not all combinations are possible.
Example: JDUGCKTN 77.76 = 3.3 volt, VCXO@77.760,
±50
ppm APR, 0/70°C,
40/60% Symmetry, CMOS, Tri-State on pin 2.
Vectron International 267 Lowell Rd. Hudson, NH 03051
Tel:1-88-VECTRON-1
5
e-mail vectron@vectron.com
PCB Design
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