K9F1G08R0A
K9F1G08U0A K9K2G08U1A
Preliminary
FLASH MEMORY
Document Title
128M x 8 Bit / 256M x 8 Bit
NAND Flash Memory
Revision History
Revision No
0.0
0.1
History
1. Initial issue
1. The tADL(Address to Data Loading Time) is added.
- tADL Minimum 100ns (Page 11, 23~26)
- tADL is the time from the WE rising edge of final address cycle
to the WE rising edge of first data cycle at program operation.
2. Added Addressing method for program operation
Draft Date
Aug. 24. 2003
Jan. 27. 2004
Remark
Advance
Preliminary
0.2
0.3
0.4
1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
1. PKG(TSOP1, WSOP1) Dimension Change
1. Technical note is changed
2. Notes of AC timing characteristics are added
3. The description of Copy-back program is changed
4. Voltage range is changed
-1.7V~1.95V -> 1.65V~1.95V
5. Note2 of Command Sets is added
1. CE access time : 23ns->35ns (p.11)
Apr. 23. 2004
May. 19. 2004
Jan. 21. 2005
Preliminary
Preliminary
Preliminary
Feb. 14. 2005
0.5
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
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K9F1G08R0A
K9F1G08U0A K9K2G08U1A
Preliminary
FLASH MEMORY
128M x 8 Bit /256M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F1G08R0A
K9F1G08U0A-Y,P
K9F1G08U0A-V,F
K9K2G08U1A-I
2.7 ~ 3.6V
Vcc Range
1.65 ~ 1.95V
X8
Organization
PKG Type
Only available in MCP
TSOP1
WSOP1
52-ULGA
FEATURES
•
Voltage Supply
-1.8V device(K9F1G08R0A): 1.65V~1.95V
-3.3V device(K9F1G08U0A): 2.7 V ~3.6 V
•
Organization
- Memory Cell Array : (128M + 4,096K)bit x 8bit
- Data Register : (2K + 64)bit x8bit
- Cache Register : (2K + 64)bit x8bit
•
Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
•
Page Read Operation
- Page Size : 2K-Byte
- Random Read : 25µs(Max.)
- Serial Access : 30ns(Min.) - 3.3v device
50ns(Min.) -1.8v device
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Cache Program Operation for High Performance Program
•
Intelligent Copy-Back Operation
•
Unique ID for Copyright Protection
•
Package :
- K9F1G08U0A-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F1G08U0A-VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F1G08U0A-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F1G08U0A-FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F1G08U0A-V,F(WSOPI ) is the same device as
K9F1G08U0A-Y,P(TSOP1) except package type.
- K9K2G08U1A-ICB0/IIB0
52-ULGA (12X17X0.65mm)
GENERAL DESCRIPTION
Offered in 128Mx8bit the K9F1G08X0A is 1G bit with spare 32M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 200µs on the 2112-byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 30ns(50ns with 1.8V
device) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the K9F1G08X0A′s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08X0A is an optimum solu-
tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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