GS841E18AT/B-180/166/150/130/100
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Dual Cycle Deselect (DCD)
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (Pentium
TM
and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA
• RoHS-compliant 100-lead TQFP and 119-bump BGA
packages available
256K x 18 Sync
Cache Tag
180 MHz–100 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
Functional Description
me
nd
ed
for
The GS841E18A is a 256K x 18 high performance synchronous DCD
SRAM with integrated Tag RAM comparator. A 2-bit burst counter is
included to provide burst interface with Pentium
TM
and other high
performance CPUs. It is designed to be used as a Cache Tag SRAM,
as well as data SRAM. Addresses, data IOs, match output, chip
enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC,
ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are
synchronous and are controlled by a positive-edge-triggered clock
(CLK).
Ne
w
Re
co
m
Output Enable (OE), Match Output Enable, and power down control
(ZZ) are asynchronous. Burst can be initiated with either ADSP or
ADSC inputs. Subsequent burst addresses are generated internally and
are controlled by ADV. The burst sequence is either interleave order
(Pentium
TM
or x86) or linear order, and is controlled by LBO.
Parameter Synopsis
–180
-166
6.0 ns
3.5 ns
310 mA
8.5 ns
10 ns
190 mA
-150
6.6 ns
3.8 ns
275 mA
10 ns
10 ns
190 mA
-133
7.5 ns
4.0 ns
250 mA
11 ns
15 ns
140 mA
-100
10 ns
4.5 ns
190 mA
12 ns
15 ns
140 mA
© 2001, GSI Technology
t
cycle
t
KQ
I
DD
t
KQ
t
cycle
I
DD
5.5 ns
3.2 ns
335 mA
8 ns
9.1 ns
210 mA
1/21
No
t
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03b 2/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
* Pentium is a trademark of Intel
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
Dual Cycle Deselect (DCD)
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT mode
pin, I/O registers can be programmed to perform pipeline or flow
through operation. Flow Through mode reduces latency.
Byte write operation is performed by using Byte Write Enable (BWE)
input combined with two individual byte write signals BW1-2. In
addition, Global Write (GW) is available for writing all bytes at one
time.
Compare cycles begin as a read cycle with output disabled so that
compare data can be loaded into the data input register. The
comparator compares the read data with the registered input data and a
match signal is generated. The match output can be either in Pipeline
or Flow Through modes controlled by the FT signal.
Low power (Standby mode) is attained through the assertion of the ZZ
signal, or by stopping the clock (CLK). Memory data is retained
during Standby mode.
JTAG boundary scan interface is provided using IEEE standard
1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out
(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to
perform JTAG function.
The GS841E18A operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output
(V
DDQ
) pins are used to allow both 3.3 V or 2.5 V IO interface.
The GS841E18A is a DCD pipelines synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. DCD SRAMs hold the deselect command for one full
cycle and then begin turning off their outputs just after the second
rising edge of the clock.
ct
GS841E18AT/B-180/166/150/130/100
TQFP Pin Description
Symbol
An
CLK
BWE
BW1
BW2
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ
DQP
MATCH
MOE
DE
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
NC
Description
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
page 11.
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
Byte Write signal for data outputs 1 thru 8
Global Write Enable
Chip Enables
Output Enable
Byte Write signal for data outputs 9 thru 16
De
sig
Data Enable—Data input registers are updated only when DE is active.
Power down control—Application of ZZ will result in a low standby power consumption.
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
3.3 V power supply
Ground
2.5 V/3.3 V output power supply
No Connect
Rev: 1.03b 2/2008
No
t
Re
co
m
me
nd
ed
for
Ne
w
4/21
n—
Di
sco
nt
inu
ed
Pr
od
u
Burst address advance
Address status signals
Data Input and Output pins
Match Output
Match Output Enable
Parity Input and Output pins
Clock Input Signal
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2001, GSI Technology
GS841E18AT/B-180/166/150/130/100
PBGA Pin Description
Symbol
An
CLK
BWE
BW1
BW2
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ
DQP
MATCH
MOE
DE
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
Description
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
page 11.
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
Byte Write signal for data outputs 1 thru 8
Global Write Enable
Chip Enables
Output Enable
Byte Write signal for data outputs 9 thru 16
De
sig
Data Enable—Data input registers are updated only when DE is active.
Power down control—Application of ZZ will result in a low standby power consumption.
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
3.3 V power supply
Ground
2.5 V/3.3 V output power supply
No Connect
V
DDQ
NC
Rev: 1.03b 2/2008
No
t
Re
co
m
me
nd
ed
for
Ne
w
5/21
n—
Di
sco
nt
inu
ed
Pr
od
u
Burst address advance
Address status signals
Data Input and Output pins
Match Output
Match Output Enable
Parity Input and Output pins
Clock Input Signal
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2001, GSI Technology
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