XCV1000E-7FG680C datasheet, PDF

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XCV1000E-7FG680C: DescriptionFPGA, 1536 CLBS, 82944 GATES, 400 MHz, PQFP240; CategoryProgrammable logic devices Programmable logic; File Size64KB，5 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XCV1000E-7FG680C Overview

FPGA, 1536 CLBS, 82944 GATES, 400 MHz, PQFP240

XCV1000E-7FG680C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	BGA
package instruction	FBGA-680
Contacts	680
Reach Compliance Code	not_compliant
ECCN code	3A991.D
maximum clock frequency	400 MHz
Combined latency of CLB-Max	0.42 ns
JESD-30 code	S-PBGA-B680
JESD-609 code	e0
length	40 mm
Humidity sensitivity level	3
Configurable number of logic blocks	6144
Equivalent number of gates	331776
Number of entries	512
Number of logical units	27648
Output times	512
Number of terminals	680
Maximum operating temperature	85 °C
Minimum operating temperature
organize	6144 CLBS, 331776 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA680,39X39,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	1.2/3.6,1.8 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.9 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	40 mm

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Virtex™-E 1.8 V

Field Programmable Gate Arrays

DS022-1 (v2.2) November 9, 2001

Preliminary Product Specification

Features

•

Fast, High-Density 1.8 V FPGA Family

- Densities from 58 k to 4 M system gates

- 130 MHz internal performance (four LUT levels)

- Designed for low-power operation

- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz

Highly Flexible SelectI/O+™ Technology

- Supports 20 high-performance interface standards

- Up to 804 singled-ended I/Os or 344 differential I/O

pairs for an aggregate bandwidth of > 100 Gb/s

Differential Signalling Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Differential I/O signals can be input, output, or I/O

- Compatible with standard differential devices

- LVPECL and LVDS clock inputs for 300+ MHz

clocks

Proprietary High-Performance SelectLink™

Technology

- Double Data Rate (DDR) to Virtex-E link

- Web-based HDL generation methodology

Sophisticated SelectRAM+™ Memory Hierarchy

- 1 Mb of internal configurable distributed RAM

- Up to 832 Kb of synchronous internal block RAM

- True Dual-Port™ BlockRAM capability

- Memory bandwidth up to 1.66 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

- Designed for high-performance Interfaces to

External Memories

- 200 MHz ZBT* SRAMs

- 200 Mb/s DDR SDRAMs

- Supported by free Synthesizable reference design

* ZBT is a trademark of Integrated Device Technology, Inc.

•

High-Performance Built-In Clock Management Circuitry

- Eight fully digital Delay-Locked Loops (DLLs)

- Digitally-Synthesized 50% duty cycle for Double

Data Rate (DDR) Applications

- Clock Multiply and Divide

- Zero-delay conversion of high-speed LVPECL/LVDS

clocks to any I/O standard

Flexible Architecture Balances Speed and Density

- Dedicated carry logic for high-speed arithmetic

- Dedicated multiplier support

- Cascade chain for wide-input function

- Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

- Internal 3-state bussing

- IEEE 1149.1 boundary-scan logic

- Die-temperature sensor diode

Supported by Xilinx Foundation™ and Alliance Series™

Development Systems

- Further compile time reduction of 50%

- Internet Team Design (ITD) tool ideal for

million-plus gate density designs

- Wide selection of PC and workstation platforms

SRAM-Based In-System Configuration

- Unlimited re-programmability

Advanced Packaging Options

- 0.8 mm Chip-scale

- 1.0 mm BGA

- 1.27 mm BGA

- HQ/PQ

0.18

m 6-Layer Metal Process

100% Factory Tested

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-1 (v2.2) November 9, 2001

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

Module 1 of 4

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