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SYS32512ZKL-30

Description
SRAM Module, 512KX32, 30ns, CMOS, PZIP72, PLASTIC, ZIP-72
Categorystorage    storage   
File Size210KB,7 Pages
ManufacturerMOSAIC
Websitehttp://www.mosaicsemi.com/
Download Datasheet Parametric View All

SYS32512ZKL-30 Overview

SRAM Module, 512KX32, 30ns, CMOS, PZIP72, PLASTIC, ZIP-72

SYS32512ZKL-30 Parametric

Parameter NameAttribute value
MakerMOSAIC
Parts packaging codeZIP
package instruction,
Contacts72
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time30 ns
JESD-30 codeR-PZIP-T72
memory density16777216 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals72
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX32
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal locationZIG-ZAG
512K x 32 SRAM MODULE
SYS32512ZK/LK - 020/025/30/35
Issue 1.2 : January 1999
Features
• Access Times of 020/025/30/35 ns.
• 72 Pin ZIP, SIMM package
5 Volt Supply ± 10%.
Low Power Dissipation:
Operational
4.4 W (maximum).
Standby (-L Version) 11 mW (maximum).
Completely Static Operation.
On-board Supply Decoupling Capacitors.
Upgrade path to SYS321000ZK/LK.
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Description
The SYS32512ZK/LK is plastic 16Mbit Static
RAM Module housed in a 72 pin plastic SIMM, ZIP
package organised as 512K x 32. The module
utilises four fast 512K x 8 SRAMs housed in SOJ
packages, mounted on one side of an FR4 epoxy
substrate to achieve a very high density module.
The module has four Chip Selects, which when
used correctly allow reading and writing to
individual bytes or words. The pins PD0-3, are
used to identify module memory density in
applications where alternative modules can be
interchanged.
Block Diagram
A0 - A18
WE
OE
Pin Definition
ZIP
512K x 8
SRAM
NC
PD3
PD0
D0
D1
D2
D3
VCC
A7
A8
A9
D4
D5
D6
D7
WE
A14
CS1
CS3
A16
GND
D16
D17
D18
D19
A10
A11
A12
A13
D20
D21
D22
D23
GND
NC
NC
SIMM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD2
GND
PD1
D8
D9
D10
D11
A0
A1
A2
D12
D13
D14
D15
GND
A15
CS2
CS4
A17
OE
D24
D25
D26
D27
A3
A4
A5
VCC
A6
D28
D29
D30
D31
A18
NC
TOP VIEW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
63
64
68
70
72
D0 - D7
CS1
512K x 8
SRAM
CS2
512K x 8
SRAM
CS3
D8 - D15
NC
NC
PD2
PD3
GND
PD0
PD1
D0
D8
D1
D9
D2
D10
D3
D11
VCC
A0
A7
A1
A8
A2
A9
D12
D4
D13
D5
D14
D6
D15
D7
GND
WE
A15
A14
CS2
CS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D16 - D23
512K x 8
SRAM
CS4
D24 - D31
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Presence Detect
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0~A18
D0~D31
CS1~4
PD0~3
WE
OE
NC
V
CC
GND
PD1=GND
PD0=PD2=PD3=OPEN
CS4
CS3
A17
A16
OE
GND
D24
D16
D25
D17
D26
D18
D27
D19
A3
A10
A4
A11
A5
A12
VCC
A13
A6
D20
D28
D21
D29
D22
D30
D23
D31
GND
A18
NC
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Package Details
Plastic 72 Pin SIMM
Plastic 72 Pin ZIP
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