INTEGRATED CIRCUITS
PCA9533
4-bit I
2
C LED dimmer
Product data
2003 Sep 19
Philips
Semiconductors
Philips Semiconductors
Product data
4-bit I
2
C LED dimmer
PCA9533
The initial setup sequence programs the two blink rates/duty cycles
for each individual PWM. From then on, only one command from the
bus master is required to turn individual LEDs ON, OFF, BLINK
RATE 1 or BLINK RATE 2. Based on the programmed frequency
and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the
LEDs to appear at a different brightness or blink at periods up to 1.6
second. The open drain outputs directly drive the LEDs with
maximum output sink current of 25 mA per bit and 100 mA per
package.
FEATURES
•
4 LED drivers (on, off, flashing at a programmable rate)
•
2 selectable, fully programmable blink rates (frequency and duty
cycle) between 0.625 and 160 Hz (1.6 seconds and
6.25 milliseconds)
•
256 brightness steps
•
Input/outputs not used as LED drivers can be used as regular
GPIOs
To blink LEDs at periods greater than 1.6 second the bus master
(MCU, MPU, DSP, chipset, etc.) must send repeated commands to
turn the LED on and off as is currently done when using normal I/O
Expanders like the Philips PCF8574 or PCA9554. Any bits not used
for controlling the LEDs can be used for General Purpose Parallel
Input/Output (GPIO) expansion which provides a simple solution
when additional I/O is needed for ACPI power switches, sensors,
pushbuttons, alarm monitoring, fans, etc.
Power On Reset (POR) initializes the registers to their default state
causing the bits to be set high (LED off).
Due to pin limitations, the PCA9533 is not featured with hardware
address pins. The PCA9533/01 and the PCA9533/02 have different
fixed I
2
C addresses allowing operation of both on the same bus.
•
Internal oscillator requires no external components
•
I
2
C interface logic compatible with SMBus
•
Internal power-on reset
•
Noise filter on SCL/SDA inputs
•
4 open drain outputs directly drive LEDs to 25 mA
•
Edge rate control on outputs
•
No glitch on power-up
•
Supports hot insertion
•
Low stand-by current
•
Operating power supply voltage range of 2.3 V to 5.5 V
•
0 to 400 kHz clock frequency
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
PIN CONFIGURATION
LED0
LED1
LED2
V
SS
1
2
3
4
8
7
6
5
V
DD
SDA
SCL
LED3
SW01035
•
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
Figure 1. Pin configuration
•
Packages offered: SO8, TSSOP8
DESCRIPTION
The PCA9533 is a 4-bit I@C & SMBus I/O expander optimized for
dimming LEDs in 256 discrete steps for Red/Green/Blue (RGB)
color mixing and back light applications.
The PCA9533 contains an internal oscillator with two user
programmable blink rates and duty cycles coupled to the output
PWM. The LED brightness is controlled by setting the blink rate high
enough (> 100 Hz) that the blinking can not be seen and then using
the duty cycle to vary the amount of time the LED is on and thus the
average current through the LED.
PIN DESCRIPTION
PIN
NUMBER
1
2
3
4
5
6
7
8
SYMBOL
LED0
LED1
LED2
V
SS
LED3
SCL
SDA
V
DD
FUNCTION
LED driver 0
LED driver 1
LED driver 2
Supply ground
LED driver 3
Serial clock line
Serial data line
Supply voltage
2003 Sep 19
2
Philips Semiconductors
Product data
4-bit I
2
C LED dimmer
PCA9533
ORDERING INFORMATION
PACKAGES
8-Pin Plastic SO
8-Pin Plastic SO
8-Pin Plastic TSSOP
TEMPERATURE RANGE
-40 to +85
°C
-40 to +85
°C
-40 to +85
°C
ORDER CODE
PCA9533D/01
PCA9533D/02
PCA9533DP/01
TOPSIDE MARK
P9533/1
P9533/2
P33/1
DRAWING NUMBER
SOT96-1
SOT96-1
SOT505-1
SOT505-1
8-Pin Plastic TSSOP
-40 to +85
°C
PCA9533DP/02
P33/2
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
I
2
C is a trademark of Philips Semiconductors Corporation.
BLOCK DIAGRAM
PCA9533
INPUT
REGISTER
SCL
INPUT
FILTERS
SDA
I
2
C-BUS
CONTROL
LED SELECT (LSx)
REGISTER
0
1
LEDx
V
DD
POWER-ON
RESET
PRESCALER 0
REGISTER
OSCILLATOR
PRESCALER 1
REGISTER
PWM0
REGISTER
PWM1
REGISTER
BLINK0
BLINK1
V
SS
NOTE: ONLY ONE I/O SHOWN FOR CLARITY
SW02046
Figure 2. Block diagram
2003 Sep 19
3
Philips Semiconductors
Product data
4-bit I
2
C LED dimmer
PCA9533
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9533/01
is shown in Figure 3 and PCA9533/02 in Figure 4.
SLAVE ADDRESS
contents of these bits will rollover to ‘000’ after the last register is
accessed.
When auto-increment flag is set (AI = 1) and a read sequence is
initiated, the sequence must start by reading a register different from
the input register (B2 B1 B0
0
0 0 0).
Only the 3 least significant bits are affected by the AI flag.
1
1
0
0
0
1
0
R/W
Unused bits must be programmed with zeroes.
INPUT — INPUT REGISTER
SW01037
bit
Default
7
0
6
0
5
0
4
0
3
X
2
X
1
X
0
X
Figure 3. Slave address — PCA9533/01
SLAVE ADDRESS
The INPUT register reflects the state of the device pins. Writes to
this register will be acknowledged but will have no effect.
PSC0 — FREQUENCY PRESCALER 0
bit
default
SW01038
1
1
0
0
0
1
1
R/W
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PSC0 is used to program the period of the PWM output.
Figure 4. Slave address — PCA9533/02
The last bit of the address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
(PSC0
)
1)
152
PWM0 — PWM REGISTER 0
The period of BLINK0
+
bit
default
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9533 which will be stored
in the Control Register.
0
0
0
AI
0
B2
B1
B0
The PWM0 register determines the duty cycle of BLINK0. The
outputs are LOW (LED on) when the count is less than the value in
PWM0 and HIGH (LED off) when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always HIGH
(LED off) .
The duty cycle of BLINK0 is: PWM0
256
PSC1 — FREQUENCY PRESCALER 1
bit
default
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
REGISTER ADDRESS
RESET STATE: 00h
AUTO-INCREMENT FLAG
SW01034
PSC1 is used to program the period of PWM output.
(PSC1
)
1)
152
PWM1 — PWM REGISTER 1
The period of BLINK1
+
Figure 5. Control register
CONTROL REGISTER DEFINITION
B2
0
0
0
0
1
1
B1
0
0
1
1
0
0
B0
0
1
0
1
0
1
REGISTER
NAME
INPUT
PSC0
PWM0
PSC1
PWM1
LS0
TYPE
READ
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
REGISTER
FUNCTION
INPUT
REGISTER
FREQUENCY
PRESCALER 0
PWM REGISTER
0
FREQUENCY
PRESCALER 1
PWM
REGISTER 1
LED SELECTOR
bit
default
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
The PWM1 register determines the duty cycle of BLINK1. The
outputs are LOW (LED on) when the count is less than the value in
PWM1 and HIGH (LED off) when it is greater. If PWM1 is
programmed with 00h, then the PWM1 output is always HIGH
(LED off).
The duty cycle of BLINK1 is: PWM1
256
LS0 — LED SELECTOR
LED3
bit
default
7
0
6
0
5
0
LED2
4
0
LED 1
3
0
2
0
LED 0
1
0
0
0
REGISTER DESCRIPTION
The lowest 3 bits are used as a pointer to determine which register
will be accessed.
If the auto-increment flag is set, the three low order bits of the
Control Register are automatically incremented after a read or write.
This allows the user to program the registers sequentially. The
2003 Sep 19
4
The LSx LED select registers determine the source of the LED data.
00 = Output is set low Hi-Z (LED off - default)
01 = Output is set low (LED on)
10 = Output blinks at PWM0 rate
11 = Output blinks at PWM1 rate
Philips Semiconductors
Product data
4-bit I
2
C LED dimmer
PCA9533
POWER-ON RESET
When power is applied to V
DD
, an internal Power On Reset holds
the PCA9533 in a reset state until V
DD
has reached V
POR
. At this
point, the reset condition is released and the PCA9533 registers are
initialized to their default states, with all outputs in the off state.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
System configuration
A device generating a message is a transmitter: a device receiving
is the receiver. The device that controls the message is the master
and the devices which are controlled by the master are the slaves
(see Figure 8).
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
S
START condition
P
STOP condition
SCL
SW00365
Figure 7. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I
2
C
MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
2003 Sep 19
5
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