Features
•
2nd Generation EE Complex Programmable Logic Devices
– 3.0V to 3.6V Operating Range with I/Os 3.3 or 5V Compliant
– 32 - 512 Macrocells with Enhanced Features
– Pin-compatible with Industry-standard Devices
– Speeds to 5 ns Maximum Pin-to-pin Delay
– Registered Operation to 225 MHz
Enhanced Macrocells with Logic Doubling
™
Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade
Logic, Plus 15 More with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
Enhanced Connectivity
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs
and I/O for µA Level Standby Current on “L” versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA
EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
•
ATF15xxAE
Family
Datasheet
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
Preliminary
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Rev. 2398B–08/01
1
ATF15xxAE Family
General
Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells
in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability.
Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel
ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling archi-
tecture consists of wider fan-in, additional routing and clock options, combined with
sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel
enhanced macrocell includes double independent buried feedback that allows designers to
pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for
later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with
no additional design effort and is highly cost effective.
The Atmel ATF15xx Family includes all popular configurations and speeds.
Table 1.
ATF15xxAE Family Device Features
Feature
Usable Gates
Macrocells
Logic Blocks
Max. # Pins
Max. User I/Os
T
PD
Grades (ns)
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
625
32
2
44
36
4, 7, 10(15)
1250
64
4
100
68
4, 7, 10(15)
2500
128
8
256
100
5, 7, 10(15)
5000
256
16
256
164
5, 7, 10(15)
10000
512
32
256
212
5, 7, 12(15)
The Atmel ATF15xxAE Family includes pin-compatible products in all popular packages.
Table 2.
ATF15xxAE Family Device Packages and Number of Signal Pins
(1)(2)
Packages
44-pin PLCC
44-pin TQFP
49-ball BGA
84-pin PLCC
100-pin TQFP
100-ball BGA
144-pin TQFP
169-ball BGA
208-pin PQFP
256-ball BGA
100
68
68
ATF1502AE(L)
36
36
ATF1504AE(L)
36
36
41
68
84
(3)
84
100
100
164
164
176
212
84
84
120
120
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
Notes:
1. Contact Atmel for up-to-date information on device and package availability.
2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing
(BST), the four associated pins become JTAG pins and are unavailable for user I/O.
3. Thermal Analysis must be performed for this package to ensure compliance with DC and AC
operating conditions. For more information, see “Thermal Characteristic’s of Atmel
Packages”.
5
2398B–08/01
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