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Freescale Semiconductor
Technical Data
Document Number: MPC852TEC
Rev. 4, 09/2007
MPC852T PowerQUICC™
Hardware Specifications
This document contains detailed information for the
MPC852T power considerations, DC/AC electrical
characteristics, AC timing specifications, and pertinent
electrical and physical characteristics. For information about
functional characteristics of the processor, refer to the
MPC866 PowerQUICC™ Family Reference Manual
(MPC866UM). The MPC852T contains a PowerPC™
processor core built on Power Architecture™ technology.
To locate published errata or updates for this document, refer
to the MPC852T product summary page on our website
listed on the back cover of this document or, contact your
local Freescale sales office.
1.
2.
3.
4.
5.
6.
7.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Calculation and Measurement . . . . . . . . . . . 9
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supply and Power Sequencing . . . . . . . . . . . 12
Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 42
CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 57
Mechanical Data and Ordering Information . . . . . . . 60
Document Revision History . . . . . . . . . . . . . . . . . . . 76
© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
Overview
1
Overview
The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC™ family, and can operate up to
100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V
I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a
versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in Ethernet control applications, including CPE equipment,
Ethernet routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
2
Features
The MPC852T is comprised of three modules that each use a 32-bit internal bus: an MPC8xx core, system
integration unit (SIU), and communication processor module (CPM).
The following list summarizes the key MPC852T features:
• Embedded MPC8xx core up to 100 MHz
• Maximum frequency operation of the external bus is 66 MHz
— 50/66 MHz core frequencies support both 1:1 and 2:1 modes
— 80/100 MHz core frequencies support 2:1 mode only
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction caches is two-way, set-associative with 128 sets
– 4-Kbyte data cachesis two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
2
Freescale Semiconductor
Features
•
•
•
•
•
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory
devices
— DRAM controller-programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
Fast Ethernet controller (FEC)
General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gate mode can enable or disable counting
— Interrupt can be masked on reference match and event capture
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1™ standard test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— Seven port pins with interrupt capability
— Eighteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest-priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT
MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Eight serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor
3
Features
•
•
•
•
•
•
•
•
Two baud rate generators
— Independent (can be connected toany SCC3/4 or SMC1)
— Allows changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3® standard optional on SCC3 and SCC4, supporting full 10-Mbps
operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Universal asynchronous receiver transmitter (UART)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
One SMC (serial management channel)
— UART
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one independent PCMCIA socket; 8-memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =
≠
< >
— Each watchpoint can generate a break point internally
Normal high and normal low power modes to conserve power
1.8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to
Table 5
for a listing of
the 5-V tolerant pins.
Figure 1
shows the MPC852T block diagram.
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
4
Freescale Semiconductor
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