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DS33R41
Inverse-Multiplexing Ethernet Mapper with
Quad Integrated T1/E1/J1 Transceivers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS33R41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four interleaved
T1/E1/J1 lines using a robust, balanced, and
programmable inverse multiplexing. Four integrated
T1/E1/J1 transceivers provide framing and line
interfacing functionality.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
committed information rate (CIR) controller provides
fractional bandwidth allocation up to the line rate in
increments of 512kbps.
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Layer 1 Inverse Multiplexing Over Four
T1/E1/J1 Lines Through the Integrated
Framers and LIUs
Supports Up to 7.75ms Differential Delay
Aggregate Bandwidth from Up to Four
T1/E1/J1 Links
T1/E1 Signaling Capability for OAM
HDLC/LAPS Encapsulation with
Programmable FCS, Interframe Fill
CIR Controller Provides Fractional
Allocations in 512kbps Increments
Programmable BERTs
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
T1/E1
LINES
FUNCTIONAL DIAGRAM
DS33R41
4 INTERLEAVED
SERIAL STREAMS
4 T1/E1/J1
TRANSCEIVERS
WITH BERTs
1.8V, 3.3V Power Supplies
IEEE 1149.1 JTAG Support
Features continued on page
11.
HDLC/X.86
ETHERNET
MAPPER
μC
SDRAM
MII/RMII
APPLICATIONS
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
10/100
MAC
10/100
ETHERNET
PHY
ORDERING INFORMATION
PART
DS33R41
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
400 BGA
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 011607
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
TABLE OF CONTENTS
1
2
DESCRIPTION ................................................................................................................................... 9
FEATURE HIGHLIGHTS.................................................................................................................. 11
2.1 G
ENERAL
...................................................................................................................................... 11
2.2 M
ICROPROCESSOR
I
NTERFACE
...................................................................................................... 11
2.3 L
INK
A
GGREGATION
(I
NVERSE
M
ULTIPLEXING
) ............................................................................... 11
2.4 HDLC E
THERNET
M
APPING
.......................................................................................................... 11
2.5 X.86 (L
INK
A
CCESS
P
ROTOCOL FOR
SONET/SDH) E
THERNET
M
APPING
....................................... 11
2.6 A
DDITIONAL
HDLC C
ONTROLLERS IN THE
I
NTEGRATED
T1/E1/J1 T
RANSCEIVER
............................ 12
2.7 C
OMMITTED
I
NFORMATION
R
ATE
(CIR) C
ONTROLLERS
.................................................................. 12
2.8 SDRAM I
NTERFACE
...................................................................................................................... 12
2.9 T1/E1/J1 F
RAMER
........................................................................................................................ 12
2.10 L
INE
I
NTERFACE
............................................................................................................................ 13
2.11 MAC I
NTERFACE
........................................................................................................................... 13
2.12 C
LOCK
S
YNTHESIZER
.................................................................................................................... 13
2.13 J
ITTER
A
TTENUATOR
..................................................................................................................... 13
2.14 S
YSTEM
I
NTERFACE
...................................................................................................................... 14
2.15 T
EST AND
D
IAGNOSTICS
................................................................................................................ 14
2.16 S
PECIFICATIONS
C
OMPLIANCE
....................................................................................................... 14
3
APPLICATIONS ............................................................................................................................... 15
4
5
6
ACRONYMS AND GLOSSARY ....................................................................................................... 16
MAJOR OPERATING MODES ........................................................................................................ 17
BLOCK DIAGRAMS......................................................................................................................... 18
6.1 F
RAMER
/LIU I
NTERIM
S
IGNALS
...................................................................................................... 20
7
PIN DESCRIPTIONS ........................................................................................................................ 21
7.1 P
IN
F
UNCTIONAL
D
ESCRIPTION
...................................................................................................... 21
8
FUNCTIONAL DESCRIPTION ......................................................................................................... 33
8.1
P
ROCESSOR
I
NTERFACE
............................................................................................................... 34
Read-Write/Data Strobe Modes............................................................................................................35
Clear on Read .......................................................................................................................................35
Interrupt and Pin Modes........................................................................................................................35
8.1.1
8.1.2
8.1.3
9
ETHERNET MAPPER ...................................................................................................................... 36
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
E
THERNET
M
APPER
C
LOCKS
......................................................................................................... 36
Serial Interface Clock Modes ................................................................................................................38
Ethernet Interface Clock Modes............................................................................................................38
9.1.1
9.1.2
R
ESETS AND
L
OW
-P
OWER
M
ODES
................................................................................................ 39
I
NITIALIZATION AND
C
ONFIGURATION
.............................................................................................. 40
G
LOBAL
R
ESOURCES
.................................................................................................................... 41
P
ER
-P
ORT
R
ESOURCES
................................................................................................................ 41
D
EVICE
I
NTERRUPTS
..................................................................................................................... 41
S
ERIAL
I
NTERFACE
........................................................................................................................ 43
L
INK
A
GGREGATION
(IMUX) .......................................................................................................... 43
Microprocessor Requirements ..............................................................................................................45
IMUX Command Protocol .....................................................................................................................46
Out of Frame (OOF) Monitoring............................................................................................................48
Data Transfer ........................................................................................................................................48
9.8.1
9.8.2
9.8.3
9.8.4
9.9 C
ONNECTIONS AND
Q
UEUES
......................................................................................................... 49
9.10 A
RBITER
....................................................................................................................................... 50
9.11 F
LOW
C
ONTROL
............................................................................................................................ 51
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
9.11.1 Full Duplex Flow Control.......................................................................................................................51
9.11.2 Half Duplex Flow Control ......................................................................................................................53
9.11.3 Host-Managed Flow Control .................................................................................................................53
9.12 E
THERNET
I
NTERFACE
P
ORT
......................................................................................................... 54
9.12.1 DTE and DCE Mode .............................................................................................................................56
9.13 E
THERNET
MAC ........................................................................................................................... 57
9.13.1 MII Mode ...............................................................................................................................................59
9.13.2 RMII Mode.............................................................................................................................................59
9.13.3 PHY MII Management Block and MDIO Interface ................................................................................60
9.14 T
RANSMIT
P
ACKET
P
ROCESSOR
.................................................................................................... 61
9.15 R
ECEIVE
P
ACKET
P
ROCESSOR
...................................................................................................... 62
9.16 X.86 E
NCODING AND
D
ECODING
.................................................................................................... 64
9.17 C
OMMITTED
I
NFORMATION
R
ATE
C
ONTROLLER
.............................................................................. 67
10 INTEGRATED T1/E1/J1 TRANSCEIVERS...................................................................................... 68
10.1
10.2
10.3
10.4
T1/E1/J1 T
RANSCEIVER
C
LOCKS
.................................................................................................. 68
P
ER
-C
HANNEL
O
PERATION
............................................................................................................ 69
T1/E1/J1 T
RANSCEIVER
I
NTERRUPTS
............................................................................................ 69
T1 F
RAMER
/F
ORMATTER
C
ONTROL AND
S
TATUS
........................................................................... 70
10.4.1 T1 Transmit Transparency....................................................................................................................70
10.4.2 AIS-CI and RAI-CI Generation and Detection ......................................................................................70
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................71
10.5 E1 F
RAMER
/F
ORMATTER
C
ONTROL AND
S
TATUS
........................................................................... 72
10.5.1 Automatic Alarm Generation.................................................................................................................73
10.6 L
OOPBACK
C
ONFIGURATIONS
........................................................................................................ 74
10.6.1 Per-Channel Payload Loopback ...........................................................................................................75
10.7 E
RROR
C
OUNTERS
........................................................................................................................ 76
10.7.1
10.7.2
10.7.3
10.7.4
Line-Code Violation Counter (TR.LCVCR) ...........................................................................................76
Path Code Violation Count Register (TR.PCVCR) ...............................................................................77
Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................78
E-Bit Counter (TR.EBCR) .....................................................................................................................78
10.8 DS0 M
ONITORING
F
UNCTION
........................................................................................................ 79
10.9 S
IGNALING
O
PERATION
................................................................................................................. 80
10.9.1
10.9.2
10.9.3
10.9.4
Processor-Based Receive Signaling ....................................................................................................80
Hardware-Based Receive Signaling .....................................................................................................81
Processor-Based Transmit Signaling ...................................................................................................82
Hardware-Based Transmit Signaling ....................................................................................................83
10.10 P
ER
-C
HANNEL
I
DLE
C
ODE
G
ENERATION
........................................................................................ 84
10.10.1 Idle-Code Programming Examples .......................................................................................................85
10.11 C
HANNEL
B
LOCKING
R
EGISTERS
................................................................................................... 86
10.12 E
LASTIC
S
TORES
O
PERATION
........................................................................................................ 86
10.12.1 Receive Side .........................................................................................................................................86
10.12.2 Transmit Side ........................................................................................................................................87
10.12.3 Elastic Stores Initialization ....................................................................................................................87
10.13 G.706 I
NTERMEDIATE
CRC-4 U
PDATING
(E1 M
ODE
O
NLY
)............................................................ 88
10.14 T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
............................................................................... 89
10.14.1 Transmit BOC .......................................................................................................................................89
10.15 R
ECEIVE
BOC .............................................................................................................................. 89
10.16 A
DDITIONAL
(S
A
)
AND
I
NTERNATIONAL
(S
I
) B
IT
O
PERATION
(E1 O
NLY
)........................................... 90
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................90
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe .......................................................90
10.17 A
DDITIONAL
HDLC C
ONTROLLERS IN
T1/E1/J1 T
RANSCEIVER
....................................................... 91
10.17.1 HDLC Configuration..............................................................................................................................91
10.17.2 FIFO Control .........................................................................................................................................93
10.17.3 HDLC Mapping......................................................................................................................................94
10.17.4 FIFO Information ...................................................................................................................................95
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.17.5 Receive Packet-Bytes Available ...........................................................................................................95
10.18 L
EGACY
FDL S
UPPORT
(T1 M
ODE
) ............................................................................................... 96
10.18.1 Overview ...............................................................................................................................................96
10.18.2 Receive Section ....................................................................................................................................96
10.18.3 Transmit Section ...................................................................................................................................97
10.19 D4/SLC-96 O
PERATION
................................................................................................................ 97
10.20 L
INE
I
NTERFACE
U
NIT
(LIU)........................................................................................................... 98
10.20.1 LIU Operation........................................................................................................................................98
10.20.2 Receiver ................................................................................................................................................98
10.20.3 Transmitter ..........................................................................................................................................100
10.21 MCLK P
RESCALER
..................................................................................................................... 101
10.22 J
ITTER
A
TTENUATOR
................................................................................................................... 101
10.23 CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
........................................................................................ 101
10.24 R
ECOMMENDED
C
IRCUITS
........................................................................................................... 102
10.25 T1/E1/J1 T
RANSCEIVER
BERT F
UNCTION
................................................................................... 107
10.25.1 BERT Status .......................................................................................................................................107
10.25.2 BERT Mapping....................................................................................................................................107
10.25.3 BERT Repetitive Pattern Set ..............................................................................................................109
10.25.4 BERT Bit Counter................................................................................................................................109
10.25.5 BERT Error Counter............................................................................................................................109
10.25.6 BERT Alternating Word-Count Rate ...................................................................................................109
10.26 P
AYLOAD
E
RROR
-I
NSERTION
F
UNCTION
(T1 M
ODE
O
NLY
) ........................................................... 110
10.26.1 Number-of-Errors Registers................................................................................................................110
10.26.2 Number of Errors Left Register ...........................................................................................................110
11
INTERLEAVED PCM BUS OPERATION....................................................................................... 111
11.1 C
HANNEL
I
NTERLEAVE
M
ODE
...................................................................................................... 111
11.2 P
ROGRAMMABLE
B
ACKPLANE
C
LOCK
S
YNTHESIZER
..................................................................... 113
11.3 F
RACTIONAL
T1/E1 S
UPPORT
..................................................................................................... 113
11.4 T1/E1/J1 T
RANSMIT
F
LOW
D
IAGRAMS
......................................................................................... 114
12 DEVICE REGISTERS..................................................................................................................... 118
12.1 R
EGISTER
B
IT
M
APS
................................................................................................................... 119
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
Global Register Bit Map ......................................................................................................................119
Arbiter Register Bit Map......................................................................................................................120
Serial Interface Register Bit Map ........................................................................................................121
Ethernet Interface Register Bit Map....................................................................................................123
MAC Register Bit Map ........................................................................................................................124
12.2 T1/E1/J1 T
RANSCEIVER
R
EGISTER
B
IT
M
AP
................................................................................ 126
12.3 G
LOBAL
R
EGISTER
D
EFINITIONS FOR
E
THERNET
M
APPER
............................................................ 131
12.4 A
RBITER
R
EGISTERS
................................................................................................................... 143
12.4.1 Arbiter Register Bit Descriptions .........................................................................................................143
12.5 S
ERIAL
I
NTERFACE
R
EGISTERS
.................................................................................................... 144
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
Serial Interface Transmit and Common Registers..............................................................................144
Serial Interface Transmit Register Bit Descriptions ............................................................................144
Transmit HDLC Processor Registers..................................................................................................145
X.86 Registers.....................................................................................................................................151
Receive Serial Interface......................................................................................................................153
12.6 E
THERNET
I
NTERFACE
R
EGISTERS
.............................................................................................. 166
12.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................166
12.6.2 MAC Registers ....................................................................................................................................177
12.7 T
RANSCEIVER
R
EGISTERS
........................................................................................................... 193
12.7.1 Number-of-Errors Left Register...........................................................................................................293
13
FUNCTIONAL TIMING ................................................................................................................... 294
13.1 MII
AND
RMII I
NTERFACES
.......................................................................................................... 294
13.2 T1 M
ODE
.................................................................................................................................... 296
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