DA7282
LRA/ERM Ultra-Low Power Haptic Driver with Multiple
Input Triggers and Integrated Waveform Memory
General Description
DA7282 is a linear resonant actuator (LRA) and eccentric rotating mass (ERM) haptic driver offering
automatic closed-loop LRA resonant frequency tracking. The feature guarantees consistency across
LRA production tolerances, operating temperature, aging, and mechanical coupling. DA7282 offers
wideband operation that fully utilizes the capabilities of newer wideband and multi-directional LRAs.
The differential output drive architecture and continuous actuator motion sensing enable efficient,
calibration-free playback and minimize software complexity, unlike many existing solutions that
require repeated manually triggered calibration to track LRA parameters. Featuring wake-up on
2
General Purpose Input (GPI) sequence triggers and/or I C activity, DA7282 automatically returns to a
low quiescent current state (typically 0.68 µA) between playbacks. In OFF mode the device
consumes only 5 nA making it suitable for low power applications.
To reduce system complexity, an integrated Waveform Memory allows haptic sequences to be pre-
loaded to DA7282. Independent sequences can be triggered, with low-latency (0.75 ms), by up to
three separate input pins without host interaction. Haptic sequences can also be streamed to
2
DA7282 from an external source via I C or pulse width modulated (PWM) signals.
DA7282 actively monitors the back electromotive force (BEMF) while continuously driving and
applies closed-loop Active Acceleration and Rapid Stopping for sharper clicks and a higher fidelity
user experience. This offers significant advantages over existing solutions that need to move into a
high-impedance state during drive to measure the BEMF, which adds a considerable amount of
inactive time to the sequence and lowers the effective click strength for a given LRA.
Key Features
■
■
■
■
■
LRA or ERM drive capability
Automatic LRA resonant frequency tracking
Wideband LRA support
I C and PWM input streaming
Low latency (0.75 ms) I C/GPI wake-up
from IDLE state, I
Q
= 0.68 µA
state, I
Q
= 0.8 mA
2
2
■
No software requirements with embedded
operation
■
Differential PWM output drive
■
Current driven system to deliver constant
actuator power
■
Ultra-low latency (0.15 ms) in STANDBY
■
Three GPI pins for triggering of up to six
independent haptic sequences
time, and frequency control
■
Automatic short circuit protection
■
Ultra-low power consumption, I
Q
= 5 nA, when
device is disabled
■
Ultra-low power consumption, I
Q
= 0.68 µA,
with state retention in IDLE state
output limiting
■
On-board Waveform Memory with amplitude,
■
Supply monitoring, reporting, and automatic
■
Active Acceleration and Rapid Stop
technology for high-fidelity haptic feedback
■
Actuator diagnostics and fault handling
■
Configurable EMI suppression
■
Open- and closed-loop modes
■
Custom wave drive support
■
Small solution footprint WLCSP or QFN
EN
VDD
Battery
Monitor
Over-
Temperature
Protection
Applications
■
■
■
■
■
■
Mobiles, wearables and hearables
Computer peripherals
Gaming
Automotive and industrial
Virtual and augmented reality controllers
Disposable consumer products
Revision 1.0
1 of 76
SCL
SDA
nIRQ
I
2
C
References
GPI_0/PWM
GPI_1
GPI_2
Resonant
Frequency
Tracking,
Active
Acceleration,
Rapid Stop,
and
Waveform
Memory
BEMF Sensing and
Actuator Diagnostics
OUTP
ERC Driver
Regulation
Loop
Short Circuit
Protection
ERC Driver
LRA/
ERM
DA7282
GND
OUTN
Datasheet
CFR0011-120-00
14-Sept-2018
© 2018 Dialog Semiconductor
DA7282
LRA/ERM Ultra-Low Power Haptic Driver with Multiple
Input Triggers and Integrated Waveform Memory
System Diagrams
VDDIO
~50Ω
VDDIO
~50Ω
VBAT
VBAT
EN
VDD
OUTP
EN
VDD
OUTP
SDA
SCL
nIRQ
Host
SDA
SCL
nIRQ
LRA/
ERM
Host
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
LRA/
ERM
OUTN
OUTN
GPI and I
2
C
VDDIO
~50Ω
I
2
C Only
VDDIO
~50Ω
VBAT
VBAT
EN
VDD
OUTP
EN
VDD
OUTP
SDA
SCL
nIRQ
Host
SDA
SCL
nIRQ
LRA/
ERM
Host
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
LRA/
ERM
OUTN
OUTN
PWM Only
VBAT
Embedded Operation
External Boost
up to 5.5V
VBST
VDDIO
~50Ω
VDDIO
~50Ω
VBAT
EN
Host
(startup
only)
VDD
OUTP
EN
VDD
OUTP
SDA
SCL
nIRQ
SDA
SCL
nIRQ
LRA/
ERM
Host
Sensor
Hub
or
Button
Press
Detect
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
DA7282
GPI_0/PWM
GPI_1
GPI_2
GND
LRA/
ERM
OUTN
OUTN
Embedded Operation
No Host
External Boost
Operation
Figure 1: System Diagrams
Datasheet
CFR0011-120-00
Revision 1.0
2 of 76
14-Sept-2018
© 2018 Dialog Semiconductor
DA7282
LRA/ERM Ultra-Low Power Haptic Driver with Multiple
Input Triggers and Integrated Waveform Memory
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 1
System Diagrams ................................................................................................................................ 2
Legal ..................................................................................................................................................... 6
Product Family ..................................................................................................................................... 6
1
2
3
Terms and Definitions ................................................................................................................... 7
Block Diagram ............................................................................................................................... 8
Pinout ............................................................................................................................................. 9
3.1 WLCSP Package .................................................................................................................. 9
3.2 QFN Package ........................................................................................................................ 9
Characteristics ............................................................................................................................ 11
4.1 Absolute Maximum Ratings ................................................................................................ 11
4.2 Recommended Operating Conditions ................................................................................. 11
4.3 Electrical Characteristics ..................................................................................................... 12
4.4 Timing Characteristics......................................................................................................... 13
4.5 Thermal Characteristics ...................................................................................................... 14
Functional Description ............................................................................................................... 15
5.1 Features Description ........................................................................................................... 15
5.2 Functional Modes ................................................................................................................ 20
5.3 Resonant Frequency Tracking ............................................................................................ 24
5.4 Active Acceleration and Rapid Stop .................................................................................... 24
5.5 Wideband Frequency Control ............................................................................................. 26
5.6 Device Configuration and Playback .................................................................................... 26
5.7 Advanced Operation ........................................................................................................... 35
5.8 Waveform Memory .............................................................................................................. 44
5.9 General Data Format .......................................................................................................... 49
2
5.10 I C Control Interface ............................................................................................................ 52
Register Overview ....................................................................................................................... 55
6.1 Register Map ....................................................................................................................... 55
6.2 Register Descriptions .......................................................................................................... 57
Package Information ................................................................................................................... 71
7.1 WLCSP Package Outline .................................................................................................... 71
7.2 QFN Package Outline ......................................................................................................... 72
7.3 Moisture Sensitivity Level.................................................................................................... 73
7.4 WLCSP Handling ................................................................................................................ 73
7.5 Soldering Information .......................................................................................................... 73
Ordering Information .................................................................................................................. 74
Application Information .............................................................................................................. 74
4
5
6
7
8
9
10 Layout Guidelines ....................................................................................................................... 75
Datasheet
CFR0011-120-00
Revision 1.0
3 of 76
14-Sept-2018
© 2018 Dialog Semiconductor
DA7282
LRA/ERM Ultra-Low Power Haptic Driver with Multiple
Input Triggers and Integrated Waveform Memory
Figures
Figure 1: System Diagrams ................................................................................................................... 2
Figure 2: DA7282 Block Diagram .......................................................................................................... 8
Figure 3: DA7282 WLCSP Pinout Diagram (Top View) ........................................................................ 9
Figure 4: DA7282 QFN Pinout Diagram (Top View) ............................................................................. 9
2
Figure 5: I C Interface Timing .............................................................................................................. 13
Figure 6: LRA Output Acceleration Swept in Frequency with Constant Power Input Signal .............. 15
Figure 7: Narrowband and Wideband LRA Response across Frequency .......................................... 16
Figure 8: Dual Mode LRA Response across Frequency ..................................................................... 16
Figure 9: System State Diagram ......................................................................................................... 20
Figure 10: Example PWM Inputs with ACCELERATION_EN = 0 ....................................................... 22
Figure 11: LRA Single Step Drive without Acceleration and Rapid Stop ............................................ 25
Figure 12: LRA Single Step with Acceleration and Rapid Stop........................................................... 25
Figure 13: Simple Drive (Top) versus Active Acceleration and Rapid Stop Enabled (Bottom) ........... 25
Figure 14: Operation in DRO Mode ..................................................................................................... 29
Figure 15: Operation in PWM Mode .................................................................................................... 30
Figure 16: Operation in RTWM Mode ................................................................................................. 31
Figure 17: Operation in ETWM Mode .................................................................................................. 33
Figure 18: Output Voltage and Current for Different AMP_PID_EN Values ....................................... 36
Figure 19: Custom Wave Point Numbering ......................................................................................... 37
Figure 20: Half-Period Control in DRO Mode ...................................................................................... 38
Figure 21: Polarity Timing Relationship ............................................................................................... 39
Figure 22: Equivalent Electrical Model of an Actuator ........................................................................ 39
Figure 23: Automatic Output Limiting .................................................................................................. 41
Figure 24: Coin ERM Physical and Electrical Summary ..................................................................... 42
Figure 25: EN Pin Control in Push-Pull Configuration (Left) and Open Drain Configuration (Right) .. 43
Figure 26: Waveform Memory Structure ............................................................................................. 44
Figure 27: Snippet Ramp and Step with ACCELERATION_EN = 1 ................................................... 45
Figure 28: Snippet Example ................................................................................................................ 46
Figure 29: Command Structure for a Single Frame ............................................................................ 46
Figure 30: Sequence Structure ........................................................................................................... 48
Figure 31: Waveform Memory Example .............................................................................................. 48
Figure 32: Overview of Data Formats with Acceleration Disabled ...................................................... 49
Figure 33: Overview of Data Formats with Acceleration Enabled ....................................................... 50
2
Figure 34: Schematic of the I C Control Interface Bus........................................................................ 52
2
Figure 35: I C START and STOP Conditions ...................................................................................... 53
2
Figure 36: I C Byte Write (SDA line) ................................................................................................... 53
2
Figure 37: Examples of the I C Byte Read (SDA line) ........................................................................ 53
2
Figure 38: Examples of I C Page Read (SDA line) ............................................................................. 54
2
Figure 39: I C Page Write (SDA line) .................................................................................................. 54
2
Figure 40: I C Repeated Write (SDA line) ........................................................................................... 54
Figure 41: WLCSP Package Outline Drawing ..................................................................................... 71
Figure 42: QFN Package Outline Drawing .......................................................................................... 72
Figure 43: External Components Diagram .......................................................................................... 74
Figure 44: WLCSP Example PCB Layout ........................................................................................... 75
Figure 45: QFN Example PCB Layout ................................................................................................ 75
Tables
Table 1: DA728x Feature Comparison .................................................................................................. 6
Table 2: WLCSP Pin Description ........................................................................................................ 10
Table 3: QFN Pin Description .............................................................................................................. 10
Table 4: Pin Type Definition ................................................................................................................ 10
Table 5: Absolute Maximum Ratings ................................................................................................... 11
Table 6: Recommended Operating Conditions ................................................................................... 11
Datasheet
CFR0011-120-00
Revision 1.0
4 of 76
14-Sept-2018
© 2018 Dialog Semiconductor
DA7282
LRA/ERM Ultra-Low Power Haptic Driver with Multiple
Input Triggers and Integrated Waveform Memory
Table 7: Current Consumption ............................................................................................................ 12
Table 8: Electrical Characteristics ....................................................................................................... 12
Table 9: Timing Characteristics ........................................................................................................... 13
2
Table 10: I C Interface Timing Requirements ..................................................................................... 13
Table 11: WLCSP Thermal Ratings .................................................................................................... 14
Table 12: QFN Thermal Ratings ......................................................................................................... 14
Table 13: Operating Modes ................................................................................................................. 21
Table 14: Haptics Event Flag Descriptions ......................................................................................... 34
Table 15: Default CUSTOM_WAVE_GEN_COEFFx Settings ............................................................ 37
Table 16: LOOP_FILT_CAP_TRIM Register Trim Settings ................................................................ 39
Table 17: LOOP_FILT_RES_TRIM Register Trim Settings ................................................................ 40
Table 18: EN Pin Control Recommended Values of R and C ............................................................. 43
Table 19: PWL Byte Structure ............................................................................................................. 45
Table 20: Bit Definitions for Frame Parameters .................................................................................. 47
Table 21: Register Map ....................................................................................................................... 55
Table 22: CHIP_REV (0x0000) ........................................................................................................... 57
Table 23: IRQ_EVENT1 (0x0003) ....................................................................................................... 57
Table 24: IRQ_EVENT_WARNING_DIAG (0x0004) .......................................................................... 57
Table 25: IRQ_EVENT_SEQ_DIAG (0x0005) .................................................................................... 58
Table 26: IRQ_STATUS1 (0x0006) ..................................................................................................... 58
Table 27: IRQ_MASK1 (0x0007) ......................................................................................................... 58
Table 28: CIF_I2C1 (0x0008) .............................................................................................................. 59
Table 29: FRQ_LRA_PER_H (0x000A) .............................................................................................. 59
Table 30: FRQ_LRA_PER_L (0x000B) ............................................................................................... 59
Table 31: ACTUATOR1 (0x000C) ....................................................................................................... 60
Table 32: ACTUATOR2 (0x000D) ....................................................................................................... 60
Table 33: ACTUATOR3 (0x000E) ....................................................................................................... 60
Table 34: CALIB_V2I_H (0x000F) ....................................................................................................... 60
Table 35: CALIB_V2I_L (0x0010) ....................................................................................................... 61
Table 36: CALIB_IMP_H (0x0011) ...................................................................................................... 61
Table 37: CALIB_IMP_L (0x0012) ...................................................................................................... 61
Table 38: TOP_CFG1 (0x0013) .......................................................................................................... 61
Table 39: TOP_CFG2 (0x0014) .......................................................................................................... 62
Table 40: TOP_CFG3 (0x0015) .......................................................................................................... 62
Table 41: TOP_CFG4 (0x0016) .......................................................................................................... 63
Table 42: TOP_INT_CFG1 (0x0017) .................................................................................................. 63
Table 43: TOP_INT_CFG6_H (0x001C) ............................................................................................. 63
Table 44: TOP_INT_CFG6_L (0x001D) .............................................................................................. 63
Table 45: TOP_INT_CFG7_H (0x001E) ............................................................................................. 63
Table 46: TOP_INT_CFG7_L (0x001F) .............................................................................................. 63
Table 47: TOP_INT_CFG8 (0x0020) .................................................................................................. 63
Table 48: TOP_CTL1 (0x0022) ........................................................................................................... 64
Table 49: TOP_CTL2 (0x0023) ........................................................................................................... 64
Table 50: SEQ_CTL1 (0x0024) ........................................................................................................... 64
Table 51: SWG_C1 (0x0025) .............................................................................................................. 65
Table 52: SWG_C2 (0x0026) .............................................................................................................. 65
Table 53: SWG_C3 (0x0027) .............................................................................................................. 65
Table 54: SEQ_CTL2 (0x0028) ........................................................................................................... 66
Table 55: GPI_0_CTL (0x0029) .......................................................................................................... 66
Table 56: GPI_1_CTL (0x002A) .......................................................................................................... 66
Table 57: GPI_2_CTL (0x002B) .......................................................................................................... 66
Table 58: MEM_CTL1 (0x002C) ......................................................................................................... 67
Table 59: MEM_CTL2 (0x002D) ......................................................................................................... 67
Table 60: ADC_DATA_H1 (0x002E) ................................................................................................... 67
Table 61: ADC_DATA_L1 (0x002F) .................................................................................................... 67
Table 62: POLARITY (0x0043)............................................................................................................ 67
Table 63: LRA_AVR_H (0x0044) ........................................................................................................ 67
Table 64: LRA_AVR_L (0x0045) ......................................................................................................... 68
Table 65: FRQ_LRA_PER_ACT_H (0x0046) ..................................................................................... 68
Datasheet
CFR0011-120-00
Revision 1.0
5 of 76
14-Sept-2018
© 2018 Dialog Semiconductor