Features
•
Utilizes the AVR
®
RISC Architecture
•
AVR – High-performance and Low-power RISC Architecture
– 89 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 12 MIPS Throughput at 12 MHz
Data and Non-volatile Program Memory
– 1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Selectable On-chip RC Oscillator for Zero External Components
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.0 mA
– Idle Mode: 0.4 mA
– Power-down Mode: <1 µA
I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP, SOIC and SSOP
Operating Voltages
– 2.7 - 6.0V (AT90S1200-4)
– 4.0 - 6.0V (AT90S1200-12)
Speed Grades
– 0 - 4 MHz, (AT90S1200-4)
– 0 - 12 MHz, (AT90S1200-12)
•
•
•
•
•
8-bit
Microcontroller
with 1K Byte
of In-System
Programmable
Flash
AT90S1200
Summary
•
•
•
Pin Configuration
Rev. 0838HS–AVR–03/02
Note: This is a summary document. A complete document is
available on our web site at
www.atmel.com
.
1
Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S1200
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with the 32 general purpose working reg-
isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Block Diagram
Figure 1.
The AT90S1200 Block Diagram
The architecture supports high-level languages efficiently as well as extremely dense
assembler code programs. The AT90S1200 provides the following features: 1K byte of
In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32
general purpose working registers, internal and external interrupts, programmable
watchdog timer with internal oscillator, an SPI serial port for program downloading and
two software selectable power-saving modes. The Idle Mode stops the CPU while allow-
2
AT90S1200
0838HS–AVR–03/02
AT90S1200
ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscilla-
tor, disabling all other chip functions until the next External Interrupt or hardware Reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip In-System Programmable Flash allows the program memory to be repro-
grammed in-system through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-
g rammable Fla sh on a mo nolithic chip, th e Atme l AT90S1 200 is a p ower fu l
microcontroller that provides a highly flexible and cost-effective solution to many embed-
ded control applications.
The AT90S1200 AVR is supported with a full suite of program and system development
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
Pin Descriptions
VCC
GND
Port B (PB7..PB0)
Supply voltage pin.
Ground pin.
Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-
put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7
are used as inputs and are externally pulled low, they will source current if the internal
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S1200 as listed
on page 30.
Port D (PD6..PD0)
Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The
Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S1200 as listed
on page 34.
RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
XTAL1
XTAL2
3
0838HS–AVR–03/02
AT90S1200 Register Summary
Address
$3F
$3E
$3D
$3C
$3B
$3A
$39
$38
$37
$36
$35
$34
$33
$32
$31
$30
$2F
$2E
$2D
$2C
$2B
$2A
$29
$28
$27
$26
$25
$24
$23
$22
$21
$20
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
$14
$13
$12
$11
$10
$0F
...
$09
$08
…
$00
Name
SREG
Reserved
Reserved
Reserved
GIMSK
Reserved
TIMSK
TIFR
Reserved
Reserved
MCUCR
Reserved
TCCR0
TCNT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
PORTD
DDRD
PIND
Reserved
Reserved
Reserved
ACSR
Reserved
Reserved
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 11
-
-
-
INT0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TOIE0
TOV0
-
-
-
page 15
page 16
page 16
-
-
-
-
SE
-
SM
-
-
-
-
CS02
ISC01
CS01
ISC00
CS00
page 18
page 21
page 22
Timer/Counter0 (8 Bits)
-
-
-
-
WDE
WDP2
WDP1
WDP0
page 23
-
-
-
-
-
EEPROM Address Register
EEPROM Data Register
-
-
EEWE
EERE
page 25
page 25
page 25
PORTB7
DDB7
PINB7
PORTB6
DDB6
PINB6
PORTB5
DDB5
PINB5
PORTB4
DDB4
PINB4
PORTB3
DDB3
PINB3
PORTB2
DDB2
PINB2
PORTB1
DDB1
PINB1
PORTB0
DDB0
PINB0
page 29
page 29
page 29
-
-
-
PORTD6
DDD6
PIND6
PORTD5
DDD5
PIND5
PORTD4
DDD4
PIND4
PORTD3
DDD3
PIND3
PORTD2
DDD2
PIND2
PORTD1
DDD1
PIND1
PORTD0
DDD0
PIND0
page 34
page 34
page 34
ACD
-
ACO
ACI
ACIE
-
ACIS1
ACIS0
page 27
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all
bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work
with registers $00 to $1F only.
4
AT90S1200
0838HS–AVR–03/02
AT90S1200
Instruction Set Summary
Mnemonic
Operands
Description
Operation
Rd
←
Rd + Rr
Rd
←
Rd + Rr + C
Rd
←
Rd - Rr
Rd
←
Rd - K
Rd
←
Rd - Rr - C
Rd
←
Rd - K - C
Rd
←
Rd
•
Rr
Rd
←
Rd
•
K
Rd
←
Rd v Rr
Rd
←
Rd v K
Rd
←
Rd
⊕
Rr
Rd
←
$FF - Rd
Rd
←
$00 - Rd
Rd
←
Rd v K
Rd
←
Rd
•
(FFh - K)
Rd
←
Rd + 1
Rd
←
Rd - 1
Rd
←
Rd
•
Rd
Rd
←
Rd
⊕
Rd
Rd
←
$FF
PC
←
PC + k + 1
PC
←
PC + k + 1
PC
←
STACK
PC
←
STACK
if (Rd = Rr) PC
←
PC + 2 or 3
Rd - Rr
Rd - Rr - C
Rd - K
if (Rr(b) = 0) PC
←
PC + 2 or 3
if (Rr(b) = 1) PC
←
PC + 2 or 3
if (P(b)= 0) PC
←
PC + 2 or 3
if (P(b) = 1) PC
←
PC + 2 or 3
if (SREG(s) = 1) then PC
←
PC + k + 1
if (SREG(s) = 0) then PC
←
PC + k + 1
if (Z = 1) then PC
←
PC + k + 1
if (Z = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 0) then PC
←
PC + k + 1
if (C = 1) then PC
←
PC + k + 1
if (N = 1) then PC
←
PC + k + 1
if (N = 0) then PC
←
PC + k + 1
if (N
⊕
V = 0) then PC
←
PC + k + 1
if (N
⊕
V = 1) then PC
←
PC + k + 1
if (H = 1) then PC
←
PC + k + 1
if (H = 0) then PC
←
PC + k + 1
if (T = 1) then PC
←
PC + k + 1
if (T = 0) then PC
←
PC + k + 1
if (V = 1) then PC
←
PC + k + 1
if (V = 0) then PC
←
PC + k + 1
if (I = 1) then PC
←
PC + k + 1
if (I = 0) then PC
←
PC + k + 1
Rd
←
(Z)
(Z)
←
Rr
Rd
←
Rr
Rd
←
K
Rd
←
P
P
←
Rr
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
I
None
Z,N,V,C,H
Z,N,V,C,H
Z,N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
# Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
4
1/2
1
1
1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
2
1
1
1
1
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add Two Registers
ADC
Rd, Rr
Add with Carry Two Registers
SUB
Rd, Rr
Subtract Two Registers
SUBI
Rd, K
Subtract Constant from Register
SBC
Rd, Rr
Subtract with Carry Two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd, K
Set Bit(s) in Register
CBR
Rd, K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
RCALL
k
Relative Subroutine Call
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd, Rr
Compare, Skip if Equal
CP
Rd, Rr
Compare
CPC
Rd, Rr
Compare with Carry
CPI
Rd, K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less than Zero, Signed
BRHS
k
Branch if Half-carry Flag Set
BRHC
k
Branch if Half-carry Flag Cleared
BRTS
k
Branch if T-Flag Set
BRTC
k
Branch if T-Flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
DATA TRANSFER INSTRUCTIONS
LD
Rd, Z
Load Register Indirect
ST
Z, Rr
Store Register Indirect
MOV
Rd, Rr
Move between Registers
LDI
Rd, K
Load Immediate
IN
Rd, P
In Port
OUT
P, Rr
Out Port
5
0838HS–AVR–03/02