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DPS512X16MKJ3-30B

Description
SRAM Module, 1MX8, 30ns, CMOS, CQMA52, J LEAD, SLCC-52
Categorystorage    storage   
File Size702KB,8 Pages
ManufacturerB&B Electronics Manufacturing Company
Download Datasheet Parametric View All

DPS512X16MKJ3-30B Overview

SRAM Module, 1MX8, 30ns, CMOS, CQMA52, J LEAD, SLCC-52

DPS512X16MKJ3-30B Parametric

Parameter NameAttribute value
Parts packaging codeQMA
package instruction,
Contacts52
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time30 ns
JESD-30 codeR-CQMA-J52
memory density8388608 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of ports1
Number of terminals52
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize1MX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Minimum standby current2 V
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal locationQUAD
Base Number Matches1
8 Megabit High Speed CMOS SRAM
DPS512X16MKn3
DESCRIPTION:
The DPS512X16MKn3 High Speed SRAM ‘’STACK’’ modules are
a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages. The module packs 8-Megabits of low-power CMOS
static RAM in an area as small as 0.549 in
2
, while maintaining a
total height as low as 0.145 inches.
The DPS512X16MKn3 STACK modules contain two individual
512K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
Straight
Leaded
Stack
FEATURES:
Organizations Available:
512K x 16 or 1 Meg x 8
Access Times: 20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Packages Available:
SLCC Stack
Straight Leaded Stack
‘’J’’ Leaded Stack
Gullwing Leaded Stack
*
Commercial and Industrial Grade only.
‘’J’’ Leaded
Stack
Gullwing
Leaded
Stack
FUNCTIONAL BLOCK DIAGRAM
A0 - A18
I/O0 - I/O15
CE0, CE1
WE
OE0, OE1
V
DD
V
SS
N.C.
PIN NAMES
Address Inputs
Data Input/Output
Low Chip Enables
Write Enable
Output Enables
Power (+5V)
Ground
No Connect
30A129-02
REV. F
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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