EEWORLDEEWORLDEEWORLD

Part Number

Search

CLP3F-A1B2C1200-FREQD18

Description
Parallel - Fundamental Quartz Crystal, 3.579545MHz Min, 4.999MHz Max
CategoryPassive components    Crystal/resonator   
File Size56KB,1 Pages
ManufacturerCardinal Components
Environmental Compliance  
Download Datasheet Parametric View All

CLP3F-A1B2C1200-FREQD18 Overview

Parallel - Fundamental Quartz Crystal, 3.579545MHz Min, 4.999MHz Max

CLP3F-A1B2C1200-FREQD18 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresAT CUT
Ageing5 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level1000 µW
frequency stability0.005%
frequency tolerance100 ppm
JESD-609 codee3
load capacitance18 pF
Manufacturer's serial numberCLP3
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency4.999 MHz
Minimum operating frequency3.579545 MHz
Maximum operating temperature70 °C
Minimum operating temperature-10 °C
physical sizeL11.1XB4.7XH4 (mm)
Series resistance200 Ω
surface mountNO
Terminal surfaceMatte Tin (Sn)
Base Number Matches1
CARDINAL COMPONENTS
Low Profile Crystals
Cardinal “AT-Strip” low profile crystals come in a variety of heights and
specifications to accommodate all of our customers’ requirements.
CLP
Series
CLP3
CLP4
CLP5
CLP6
3.579545
D18
Part Numbering Example: CLP X - A1 B2 C2 200 - 3.579545 D18 - 3
CLP
SERIES
CLP
CLP3
CLP4
CLP5
CLP6
X
ADDED FEATURES
F = FORMED LEADS
W = VINYL SLEEVING
X = INSULATOR PAD
Y = THIRD LEAD
Z = TAPE AND REEL
BLANK = BULK PACK
A1*
B2
C2
200
-3
OPERATING TEMP. STABILITY TOLERANCE RESISTANCE FREQUENCY
LOAD CAP.
OVERTONE
BLANK: FUND.
D16,18,20,ETC.
A0 = -10°C ~ +60°C B1 = ±100 C1 = ±100 SEE CHART
-3: 3rd OT
DS = SERIES
BELOW
A1 = -10°C ~ +70°C B2 = ± 50 C2 = ± 50
-5: 5th OT
A2 = -40°C ~ +85°C B3 = ± 30 C3 = ± 30
-7: 7th OT
A3 = -55°C ~ +125°C B4 = ± 10 C4 = ± 10
-BT: BT Cut
*NOTE:
The above ABC combinations cover basic specification options. We tailor our crystal specifications
to meet customer requirements. Please contact our sales department if you don’t see exactly what you need.
Specifications:
CLP
Frequency Range:
3.579545 ~ 38.000 MHz
25.000000 ~ 75.000 MHz
26.000000 ~ 42.000 MHz
Operating Temperature:
Frequency Stability:
-10°C ~ +70°C
-40°C ~ +85°C
±100
± 50
± 30
± 15
±100
± 50
± 30
± 10
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
AT Cut Fundamental
AT Cut 3rd Overtone
BT Cut Fundamental
Standard
Standard
Frequency Tolerance:
(at 25°C)
Standard
Load Capacitance:
Resistance:
Standard:
Standard 18 pF or series.
Please specify your required load.
Maximum resistance corresponds to frequency.
See chart below.
Mode: Fundamental or 3rd Overtone
Shunt Capacitance: 7 pF Max
Aging: ± 5 ppm/year
Drive Level: 1.0 mW Max
Formed Leads
Vinyl Sleeves
Insulator Pads
Radial Tape and Reel
CLP3
Optional Features:
Note 1: Not all combinations of the above tolerances, stabilities, and temperature
ranges are available. Consult the factory if your requirement is not standard.
Note 2: Heights of 3.5 mm (0.138) and 2.5 mm (0.098) are also available. Please
consult factory if required.
Resistance Chart:
All resistances are maximum values.
EQUIVALENT SERIES RESISTANCE (ESR), MODE OF OPERATION (MODE), AND CUT
Frequency MHz
3.579545~4.999
5.000~5.999
6.000~7.999
8.000~8.999
9.000~9.999
10.000~14.999
ESR(Ω)
200 Max
150 Max
120 Max
90 Max
80 Max
70 Max
Mode/cut
Fund./AT
Fund./AT
Fund./AT
Fund./AT
Fund./AT
Fund./AT
Frequency MHz
15.000~15.999
16.000~23.999
24.000~30.000
24.000~48.000
24.576~29.999
30.000~75.000
ESR (Ω)
60 Max
50 Max
40 Max
40 Max
150 Max
100 Max
Mode/cut
Fund./AT
Fund./AT
Fund./AT
Fund./BT
3rd Overtone/AT
3rd Overtone/AT
Cardinal Components, Inc., 155 Rt. 46 W, Wayne, NJ. 07470 TEL: (973)785-1333 FAX: (973)785-0053
http://www.cardinalxtal.com
E-Mail: cardinal@cardinalxtal.com
12
an433 Source Synchronous Interface Timing Analysis
...
至芯科技FPGA大牛 FPGA/CPLD
GD32L233C-START Review——03_1.CoreMark Test, RT-Thread-Nano Porting
[i=s]This post was last edited by wadeRen on 2022-1-21 11:15[/i]Preface02_1 and 02_2 show the construction environment and a simple debugging introduction.GD32L233C- START Evaluation——02_1. Build deve...
wadeRen GD32 MCU
Transfer: Deep digging into the IAR startup function process and its underlying initialization design
Hello everyone, I am Pi Ziheng, a serious technical guy. Today, Pi Ziheng will share with you the IAR startup function flow and the impact of its __low_level_init design on function redirection . In t...
freebsder ARM Technology
TMS320C6000 Basic Learning (6) - gel file
What is a gel file? What can a gel file do? GEL stands for General Extended Language, which is a general extended language file. The GEL file is composed of codes similar to C language. GEL language i...
fish001 Microcontroller MCU
[National Technology M4 core hot-selling N32G45XVL evaluation] Part 3 DAC output dual-channel triangle wave signal
I found some time to work on the board during the Spring Festival holiday. I looked at the use of the DAC module and made an example of using DAC to output a dual-channel triangle wave signal.The foll...
oxygen_sh Domestic Chip Exchange
Doubts about LDO power supply power and output current.
[i=s]This post was last edited by SHU_2017 on 2018-12-5 08:49[/i] Background: I designed a vehicle controller to control the movement of three motors. I have encountered the problem of insufficient po...
SHU_2017 Power technology

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号