Preliminary Technical Data
FEATURES
Narrow body SOIC 8-lead package
Low power operation
5 V operation:
1.1 mA per channel max. @ 0–2 Mbps
3.7 mA per channel max. @ 10 Mbps
10 mA per channel max @ 30 Mbps
3 V operation:
0.8 mA per channel max. @ 0–2 Mbps
2.2 mA per channel max. @ 10 Mbps
6.3 mA per channel max. @ 30 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
High data rate: DC–30 Mbps (NRZ)
Precise timing characteristics:
3 ns max. pulsewidth distortion
3 ns max. channel-to-channel matching
High common-mode transient immunity: > 25 kV/μs
Safety and regulatory approvals (pending)
UL recognition
2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01
DIN EN 60950 (VDE 0805):2001-12;EN 60950:2000
V
IORM
= 560 V peak
Dual-Channel Digital Isolators
ADuM1200/ADuM1201
DESCRIPTION
The ADuM120x are two-channel digital isolators based on
Analog Devices’
iCoupler®
technology. Combining high speed
CMOS and monolithic transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes,
iCoupler
devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple,
iCoupler
digital interfaces and stable performance
characteristics. The need for external drivers and other discretes
is eliminated with these
iCoupler
products. Furthermore,
iCoupler
devices run at one-tenth to one-sixth the power
consumption of optocouplers at comparable signal data rates.
The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see Ordering Guide). Both ADuM120x models operate with
the supply voltage of either side ranging from 2.7 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling a voltage translation functionality across the isolation
barrier. In addition, the ADuM120x provides low pulsewidth
distortion (<3 ns for CRW grade), and tight channel-to-channel
matching (<3 ns for CRW grade). Unlike other optocoupler
alternatives, the ADuM120x isolators have a patented refresh
feature that ensures dc correctness in the absence of input logic
transitions and during power-up/power-down conditions.
APPLICATIONS
Size-critical multichannel isolation
SPI® interface/data converter isolation
RS-232/422/485 transceiver isolation
Digital fieldbus isolation
FUNCTIONAL BLOCK DIAGRAMS
V
dd1
1
V
IA
2
V
IB
3
GND
1
4
ENCODE
ENCODE
DECODE
DECODE
8
V
dd2
7
V
OA
6
V
OB
5
GND
2
V
dd1
1
V
OA
2
V
IB
3
GND
1
4
DECODE
ENCODE
ENCODE
DECODE
8
V
dd2
7
V
IA
6
V
OB
5
GND
2
Figure 1. ADuM1200 Functional Block Diagram
Figure 2. ADuM1201 Functional Block Diagram
Rev. PrD December 4, 2003
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
ADuM1200/ADuM1201
TABLE OF CONTENTS
Features .......................................................................................... 1
Applications................................................................................... 1
DESCRIPTION............................................................................. 1
FUNCTIONAL BLOCK DIAGRAMS ...................................... 1
Electrical Characteristics—5 V Operation
1
................................... 3
Electrical Characteristics—3 V Operation
1
................................... 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation
1
......................................................................................... 7
Package Characteristics.................................................................. 10
Regulatory Information ................................................................. 11
Insulation and Safety-Related Specifications.......................... 11
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 12
Recommended Operation Conditions.......................................... 12
Preliminary Technical Data
Absolute Maximum Ratings ......................................................... 13
Pin Configurations And Pin Function Descriptions ................. 14
Pin Configurations..................................................................... 14
Pin Function Descriptions ........................................................ 14
Typical Performance Characteristics ........................................... 15
Application Information................................................................ 16
PC Board Layout ........................................................................ 16
Propagation Delay-Related Parameters................................... 16
DC Correctness and Magnetic Field Immunity..................... 16
Power Consumption .................................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide............................................................................... 18
REVISION HISTORY
Revision 0: Initial Version
Rev. PrD| Page 2 of 18
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS—5 V OPERATION
1
ADuM1200/ADuM1201
4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V. All Min/Max specifications apply over the entire recommended operation range unless
otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1200, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
30 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM1201, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
30 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Symbol
I
DDI(Q)
I
DDO(Q)
Min.
Typ
0.50
0.19
Max
0.6
0.25
Unit
mA
mA
Test Conditions
I
DD1(Q)
I
DD2(Q)
I
DD1(10)
I
DD2(10)
I
DD1(30)
I
DD2(30)
1.1
0.5
4.3
1.3
12
3.3
1.4
0.7
5.5
1.8
16
4.0
mA
mA
mA
mA
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
15 MHz logic signal freq.
15 MHz logic signal freq.
I
DD1(Q)
I
DD2(Q)
I
DD1(10)
I
DD2(10)
I
DD1(30)
I
DD2(30)
I
IA
, I
IB
–10
V
IH
0.7V
DD
V
IL
V
OAH
, V
OBH
V
DD1,2
– 0.1
V
DD1,2
– 0.4
V
OAL
, V
OBL
0.8
0.8
2.8
2.8
7.5
7.5
0.01
1.1
1.1
3.5
3.5
9.5
9.5
10
0.3V
DD
mA
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
V
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
15 MHz logic signal freq.
15 MHz logic signal freq.
0 ≤ V
IA
, V
IB
≤ V
DD1
or V
DD2
5.0
4.8
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox
= –20 µA, V
Ix
= V
IxH
I
Ox
= –4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Rev. PrD | Page 3 of 18
ADuM1200/ADuM1201
Parameter
SWITCHING SPECIFICATIONS
ADuM120xARW
Minimum Pulsewidth
3
Maximum Data Rate
4
Propagation Delay
5
Pulsewidth Distortion, |t
PLH
-t
PHL
|
5
Propagation Delay Skew
6
Channel-to-Channel Matching
7
Output Rise/Fall Time (10%–90%)
ADuM120xBRW
Minimum Pulsewidth
3
Maximum Data Rate
4
Propagation Delay
5
Pulsewidth Distortion, |t
PLH
– t
PHL
|
5
Change Versus Temperature
Propagation Delay Skew
6
Channel-to-Channel Matching, Co-Directional
Channels
7
Channel-to-Channel Matching, Opposing-Directional
Channels
7
Output Rise/Fall Time (10%–90%)
ADuM120xCRW
Minimum Pulsewidth
3
Maximum Data Rate
4
Propagation Delay
5
Pulsewidth Distortion, |t
PLH
– t
PHL
|
5
Change Versus Temperature
Propagation Delay Skew
6
Channel-to-Channel Matching, Co-Directional
Channels
7
Channel-to-Channel Matching, Opposing-Directional
Channels
7
Output Rise/Fall Time (10%–90%)
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Common-Mode Transient Immunity at Logic High
Output
8
Common-Mode Transient Immunity at Logic Low
Output
8
Refresh Rate
Input Dynamic Supply Current, per Channel
9
Output Dynamic Supply Current, per Channel
9
Symbol
Min.
Typ
Max
Preliminary Technical Data
Unit
Test Conditions
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
t
R
/t
F
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
F
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
F
t
PHZ
, t
PLH
t
PZH
, t
PZL
|CM
H
|
|CM
L
|
f
r
I
DDI(D)
I
DDO(D)
25
25
2.5
3
3
35
35
1.2
0.19
0.05
30
20
2.5
20
50
10
20
5
1
50
1000
100
40
50
50
10
100
50
3
15
3
15
ns
Mbps
ns
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1/DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
33
45
3
5
15
3
15
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
5
5
ns
ns
kV/µs
kV/µs
Mbps
mA/Mbps
mA/Mbps
Rev. PrD| Page 4 of 18
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS—3 V OPERATION
1
ADuM1200/ADuM1201
2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V. All Min/Max specifications apply over the entire recommended operation range unless
otherwise noted. All typical specifications are at T
A
= 25
°C,
V
DD1
= V
DD2
= 3.0 V.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1200, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
30 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM1201, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
30 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Symbol
I
DDI(Q)
I
DDO(Q)
Min.
Typ
0.26
0.11
Max
0.35
0.20
Unit
mA
mA
Test Conditions
I
DD1(Q)
I
DD2(Q)
I
DD1(10)
I
DD2(10)
I
DD1(30)
I
DD2(30)
0.6
0.2
2.2
0.7
6.2
1.8
1.0
0.5
3.4
1.0
10.0
2.5
mA
mA
mA
mA
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
15 MHz logic signal freq.
15 MHz logic signal freq.
I
DD1(Q)
I
DD2(Q)
I
DD1(10)
I
DD2(10)
I
DD1(30)
I
DD2(30)
I
IA
, I
IB
–10
V
IH
0.7V
DD
V
IL
V
OAH
, V
OBH
V
DD1,2
– 0.1
V
DD1,2
– 0.4
V
OAL
, V
OBL
,
0.4
0.4
1.5
1.5
4.0
4.0
0.01
0.8
0.8
2.2
2.2
6.2
6.2
10
0.3V
DD
mA
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
15 MHz logic signal freq.
15 MHz logic signal freq.
0 ≤ V
IA
, V
IB
, ≤ V
DD1
or V
DD2
3.0
2.8
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox
= –20 µA, V
Ix
= V
IxH
I
Ox
= –4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Rev. PrD | Page 5 of 18
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