September 2001
AS6VA25616
2.7V to 3.3V 256K × 16 Intelliwatt™ low-power CMOS SRAM with one chip enable
Features
• AS6VA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 2.7V to 3.3V at 55 ns
• Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
• ESD protection
≥
2000 volts
• Latch-up current
≥
200 mA
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• Low power consumption: STANDBY
- 66 µW max at 3.3V
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
Row Decoder
V
CC
256K × 16
Array
(4,194,304)
V
SS
Pin arrangement (top view)
44-pin 400-mil TSOP 2
A4
1
44
A5
A3
2
A6
43
42
A2
3
A7
41
A1
4
OE
A0
5
40
UB
CS
6
39
LB
I/O16
7
38
I/O1
I/O15
8
37
I/O2
I/O14
9
36
I/O3
I/O13
10
35
I/O4
V
CC
V
SS
11
34
V
SS
V
CC
12
33
I/O5
13
32
I/O12
I/O6
14
31
I/O11
15
I/O7
30
I/O10
16
I/O8
29
I/O9
17
28
WE
NC
18
27
A8
A17
19
26
A9
A16
20
25
A10
A15
24
A11
A14
21
23
A12
A13
22
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
V
SS
V
CC
I/O15
I/O16
NC
2
3
OE
A0
A3
UB
I/O11 A5
I/O12 A17
I/O13 NC
I/O14 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
V
CC
V
SS
I/O7
I/O8
NC
Selection guide
V
CC
Range
Product
AS6VA25616
Min
(V)
2.7
Typ
2
(V)
3.0
Max
(V)
3.3
Speed
(ns)
55
Power Dissipation
Operating (I
CC
)
Max (mA)
2
Standby (I
SB1
)
Max (
µ
A)
20
9/25/01; v.1.3
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS6VA25616
Functional description
The AS6VA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits.
It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit
easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6VA25616 is guaranteed not to exceed 66
µW
power
consumption at 3.3V and 55 ns. The device also returns data when V
CC
is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or
(UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the JEDEC standard
400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Device
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
1.0
+150
+125
20
Max
V
CC
+ 0.5
Unit
V
V
W
o
C
o
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
H
L
L
L
WE
X
X
H
H
OE
X
X
H
L
LB
X
H
X
L
H
L
L
L
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
H
X
H
L
L
H
L
L
Supply
Current
I
SB
I
CC
I
CC
I/O1–I/O8 I/O9–I/O16
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Mode
Standby (I
SB
)
Output disable (I
CC
)
Read (I
CC
)
I
CC
High Z
D
IN
Write (I
CC
)
9/25/01; v.1.3
Alliance Semiconductor
P. 2 of 10
AS6VA25616
Write cycle (over the operating range)
Parameter
Write cycle time
Chip select to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
Min
55
40
40
0
35
0
0
25
0
0
5
35
Max
–
–
–
–
–
–
–
–
–
20
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
12
4, 5
4, 5
4, 5
Write waveform 1 (WE controlled)
t
WC
Address
t
CW
CS
t
BW
LB, UB
t
AS
WE
t
DW
D
IN
D
OUT
Data undefined
t
WZ
Data valid
t
OW
High Z
t
DH
t
AW
t
WP
t
AH
t
WR
Write waveform 2 (CS controlled)
t
WC
Address
t
AS
CS
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
D
IN
D
OUT
t
CLZ
High Z
t
WZ
Data undefined
Data valid
t
OW
High Z
t
DH
t
AH
t
WR
9/25/01; v.1.3
Alliance Semiconductor
P. 5 of 10
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