V58C2256(804/404/164)SH
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
4
DDR500
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
5ns
5ns
4ns
250 MHz
5
DDR400
7.5ns
6ns
5ns
200 MHz
6
DDR333
7.5ns
6ns
6ns
166 MHz
Features
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-
Description
The V58C2256(804/404/164)SH is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SH achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the out-
put data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock.
I/O transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A
sequential and gapless data rate is possible depending
on burst length, CAS latency and speed grade of the
device.
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High speed data transfer rates with system
frequency up to 250 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V for all products
tRAS lockout supported
Concurrent auto precharge option is supported
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
•
CK Cycle Time (ns)
-4
•
•
Power
Std.
•
•
-5
•
•
-6
•
•
L
•
•
Temperature
Mark
Blank
I
V58C2256(804/404/164)SH Rev.1.1 July 2010
1
ProMOS TECHNOLOGIES
Block Diagram
V58C2256(804/404/164)SH
64M x 4
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
RAS
CAS
WE
CK
CK
DLL
Strobe
Gen.
CS
CK, CK
CKE
DM
DQS
Data Strobe
V58C2256(804/404/164)SH Rev. 1.1 July 2010
5
Development Kits Review Area
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