The Maverick™ EP7309 is designed for ultra-low-power
applications such as digital music players, internet
appliances, smart cellular phones or any hand-held
device that features the added capability of digital audio
decompression. The core-logic functionality of the device
is built around an ARM720T processor with 8 KB of four-
way set-associative unified cache and a write buffer.
Incorporated into the ARM720T is an enhanced memory
management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft
®
Windows
®
CE and Linux
®
.
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
Power
Management
EPB Bus
Clocks &
Timers
ICE-JTAG
SERIAL PORTS
Serial
Interface
ARM720T
ARM7TDMI CPU Core
Interrupts,
PWM & GPIO
USER INTERFACE
(2) UARTs
w/ IrDA
Internal Data Bus
Boot
ROM
8 KB
Write
Cache
Buffer
MMU
Bus
Bridge
Keypad&
Touch
Screen I/F
MaverickKey
TM
SRAM &
FLASH I/F
On-chip SRAM
48 KB
LCD
Controller
MEMORY AND STORAGE
Copyright 2001 Cirrus Logic (All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
June ’01
DS507PP1
1
EP7309
High-Performance, Low-Power System on Chip
FEATURES
(cont)
I
Dynamically programmable clock speeds of 18, 36, 49,
and 74 MHz
I
48 KB of on-chip SRAM
I
MaverickKey™ IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
I
LCD controller
— Interfaces directly to a single-scan panel
monochrome STN LCD
— Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
I
Full JTAG boundary scan and Embedded ICE
support
I
Integrated Peripheral Interfaces
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Digital Audio Interface providing glueless
interface to low-power DACs, ADCs and CODECs
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
I
Internal Peripherals
— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
I
Package
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
I
The fully static EP7309 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
OVERVIEW
(cont.)
The EP7309 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V. The device has three basic
power states: operating, idle and standby.
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality
audio converters. In particular, the DAI can directly
interface with the Crystal‚ CS43L41/42/43 low-power
audio DACs and the Crystal‚ CS53L32 low-power ADC.
Some of these devices feature digital bass and treble
boost, digital volume control and compressor-limiter
functions.
Simply by adding desired memory and peripherals to the
highly integrated EP7309 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de-
scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property
of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from
any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore,
no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus
Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7309 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Entries
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7309 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7309 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
Memory Interfaces
The EP7309 is equiped with a ROM/SRAM/FLASH-
style interface that has programmable wait-state timings
and includes burst-mode capability, with six chip selects
decoding six 256 MB sections of addressable space. For
maximum flexibility, each bank can be specified to be 8-,
16-, or 32-bits wide. This allows the use of 8-bit-wide
boot ROM options to minimize overall system cost. The
on-chip boot ROM can be used in product manufacturing
to serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.
Pin Mnemonic
nCS[5:0]
A[27:0]
D[31:0]
Power Management
The EP7309 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
I/O
O
O
I/O
O
O
O
O
O
Pin Description
Chip select out
Address output
Data I/O
ROM expansion OP enable
ROM expansion write enable
Halfword access select
output
Word access select output
Transfer direction
Pin Mnemonic
BATOK
nEXTPWR
nPWRFL
nBATCHG
I/O
I
I
I
I
Pin Description
Battery ok input
External power supply sense
input
Power fail sense input
Battery changed sense input
nMOE
nMWE
HALFWORD
WORD
WRITE
Table A. Power Management Pin Assignments
Table B. Static Memory Interface Pin Assignments
MaverickKey
™
Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
DS507PP1
Digital Audio Capability
The EP7309 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7309
Copyright 2001 Cirrus Logic (All Rights Reserved)
3
EP7309
High-Performance, Low-Power System on Chip
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7309 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
TXD[1]
RXD[1]
CTS
DCD
DSR
TXD[2]
RXD[2]
LEDDRV
PHDIN
CODEC Interface
The EP7309 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the DAI and
SSI2.
Pin Mnemonic
PCMCLK
PCMOUT
PCMIN
PCMSYNC
I/O
O
O
I
O
Pin Description
Serial bit clock
Serial data out
Serial data in
Frame sync
I/O
O
I
I
I
I
O
I
O
I
Pin Description
UART 1 transmit
UART 1 receive
UART 1 clear to send
UART 1 data carrier detect
UART 1 data set ready
UART 2 transmit
UART 2 receive
Infrared LED drive output
Photo diode input
Table E. CODEC Interface Pin Assignments
Note:
See
Table Q on page 7
for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the DAI and CODEC interfaces through a multiplexer.
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for
asymmetric traffic
Table C. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Digital Audio Interface (DAI)
The EP7309 integrates an interface to enable a direct
connection to many low cost, low power, high quality
audio converters. In particular, the DAI can directly
interface with the Crystal
‚
CS43L41/42/43 low-power
audio DACs and the Crystal
‚
CS53L32 low-power ADC.
Some of these devices feature digital bass and treble
boost, digital volume control and compressor-limiter
functions.
Pin Mnemonic
SCLK
SDOUT
SDIN
LRCK
MCLKIN
MCLKOUT
Pin Mnemonic
SSICLK
SSITXDA
SSIRXDA
I/O
I/O
O
I
I/O
I/O
Pin Description
Serial bit clock
Serial data out
Serial data in
Transmit frame sync
Receive frame sync
I/O
O
O
I
O
I
O
Pin Description
Serial bit clock
Serial data out
Serial data in
Sample clock
Master clock input
Master clock output
SSITXFR
SSIRXFR
Table F. SSI2 Interface Pin Assignments
Note:
See
Table Q on page 7
for information on pin
multiplexes.
Table D. DAI Interface Pin Assignments
Note:
See
Table Q on page 7
for information on pin
multiplexes.
4
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Synchronous Serial Interface
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Pin Mnemonic
ADCLK
ADCIN
ADCOUT
nADCCS
SMPCLK
I/O
O
I
O
O
O
Pin Description
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
• Column outputs can be individually set high with the
remaining bits left at high-impedance
• Column outputs can be driven all-low, all-high, or all-
high-impedance
• Keyboard interrupt driven by OR'ing together all Port
A bits
• Keyboard interrupt can be used to wake up the
system
• 8
×
8 keyboard matrix usable with no external logic,
extra keys can be added with minimal glue logic
Pin Mnemonic
COL[7:0]
I/O
O
Pin Description
Keyboard scanner column drive
Table G. Serial Interface Pin Assignments
Table I. Keypad Interface Pin Assignments
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
• Interfaces directly to a single-scan panel monochrome
STN LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024
pixels in 16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7309 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
• Supports 22 interrupts from a variety of sources (such
as UARTs, SSI1, and key matrix.)
• Routes interrupt sources to the ARM720T’s IRQ or
FIQ (Fast IRQ) inputs
• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
.
Pin Mnemonic
CL1
CL2
DD[3:0]
FRM
M
I/O
O
O
O
O
O
Pin Description
LCD line clock
LCD pixel clock out
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
Pin Mnemonic
nEINT[2:1]
EINT[3]
nEXTFIQ
nMEDCHG/nBROM
(Note)
I/O
I
I
I
I
Pin Description
External interrupt
External interrupt
External Fast Interrupt input
Media change interrupt input
Table H. LCD Interface Pin Assignments
Table J. Interrupt Controller Pin Assignments
Note:
Pins are multiplexed. See
Table R on page 7
for more
information.
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7309. A dedicated 8-bit column driver output
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively OR'ed together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
DS507PP1
Real-Time Clock
The EP7309 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
京公网安备 11010802033920号
EEWORLD
