GS8342R09E-333I datasheet, PDF

Datasheet> All Categories > storage> storage> GS8342R09E-333I

GS8342R09E-333I: DescriptionDDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165; Categorystorage storage; File Size2MB，37 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

Download Datasheet Parametric View All

GS8342R09E-333I Overview

DDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, BGA-165

GS8342R09E-333I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	BGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX9
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Preliminary

GS8342R08/09/18/36E-333/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) and Nybble Write (x8) function

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

36Mb SigmaCIO DDR-II

Burst of 4 SRAM

167 MHz–333 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs

always transfer data in four packets. When a new address is

loaded, A0 and A1 preset an internal 2 bit linear address

counter. The counter increments by 1 for each beat of a burst of

four data transfer. The counter always wraps to 00 after

reaching 11, no matter where it starts.

Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer

data in four packets. When a new address is loaded, the LSBs

are internally set to 0 for the first read or write transfer, and

incremented by 1 for the next 3 transfers. Because the LSBs

are tied off internally, the address field of a x8 SigmaCIO

DDR-II B4 RAM is always two address pins less than the

advertised index depth (e.g., the 8M x 8 has a 1M addressable

index).

SigmaCIO™ Family Overview

The GS8342R08/09/18/36E are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342R08/09/18/36E SigmaCIO SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342R08/09/18/36E SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Parameter Synopsis

-333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.02 8/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

Digital tachometer circuit diagram based on magnetic sensor design

Continuous casting machine motor speed regulation trigger circuit

Crystal diode three-phase bridge resistive load rectifier circuit

Optocoupler test circuit

555 multifunctional home appliance protector circuit (1)

810 computer motherboard circuit diagram_36

Two small questions about the C5509A debugging process: [size=4]Share 2 small problems about the debugging process of C5509A. The solutions are as follows[/size] [size=4] [/size] [size=4](1) Error Trouble Writing Register: Error 0x00000004---1024 Error dur...; Jacktang DSP and ARM Processors

DSP assembly feels difficult to start: I am a DSP optimization engineer. I am currently using c66. I want to optimize from the assembly perspective. Can anyone with experience give me some advice? I don't know where to start. The resource ...; 飞哥传输 DSP and ARM Processors

TMS320C6678 external memory DDR3 hardware design and software debugging: 1. Hardware DesignThis design refers to the sample design of TI. On the basis of the sample, in order to save cost and space, the ECC of DDR3 is deleted. Only 4 pieces of Samsung's K4B1G1646G are left...; Aguilera DSP and ARM Processors

Questions about using an oscilloscope differential probe to measure the voltage across a resistor and calculate the current: Due to the limited instruments at hand, I plan to use a differential probe to measure the voltage across the resistor as shown in the figure below, so as to calculate the laser current. There are two ...; xiaxingxing Analog electronics

Automatic power off function when not in use for a long time: There is a circuit that can automatically shut off the power if not used for a long time. How is it controlled? Its main chip is EC51925A. This chip should be controlled by a certain pin, but I don't ...; zk643 MCU

What is SDR? Software Radio Basics: From military and aerospace to hobbyists, the promise of software-defined radio (SDR) is that with a single piece of hardware, users can capture, demodulate, and access RF signals across a wide range ...; Jacktang RF/Wirelessly

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components