SED1180
SED1180
CMOS LCD 64-SEGMENT DRIVER
s
DESCRIPTION
The SED1180 is a dot matrix LCD segment (column) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI contains 64-bit shift register for display data. The display data is supplied through
4-bit bus, and serially transferred through 16
×
4 bit shift register. The display data is held in a 64-bit latch
circuit. The LSI converts the level of the latched data to an LCD drive waveform.
The SED1180 is used in conjunction with the SED1190 (64-bit row driver) to drive a large-capacity dot matrix
LCD panel.
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FEATURES
•
Low-power CMOS technology
•
64-bit segment (column) driver
•
High-speed 4-bit data
•
Duty cycle ..................................... 1/64 to 1/128
•
Daisy chain enable support
s
SYSTEM BLOCK DIAGRAM
•
Wide range of LCD voltage .......... –14V to –25V
•
Supply voltage .................................. 5.0V
±10%
QFP1-80 pin (F
•
Package ................................ QFP5-80 pin (F ))
0A
5A
DIE: Al pad chip (D
0A
)
D0 ~ D3
XSCL
LP, FR
YSCL
YD
LCD
CONTR
SED1180
64
SED1180
64
SED1180
64
SED1180
64
SED1190
64
256 SEG
×
64 COM
DUTY: 1/64
425
SED1180
s
BLOCK DIAGRAM
0
D0
D1
D2
D3
LP
XSCL
4
1
SEG
31
LCD Driver
Level Shifter
Latch
Shift Register
32 bits
32 bits
32 bits
32 bits
4
Voltage Control
EI
ECL
Enable
Control
Shift Register
Latch
FR
V
SS
V
DD
V2
V3
V
SSH
5
Level Shifter
LCD Driver
32 bits
32 bits
32 bits
32 bits
EO
TEST
32
33
SEG
63
s
PIN CONFIGURATION
64
41
65
40
SED1180
80
25
1
24
426
SED1180
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG 9
SEG 8
Number
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
SEG 7
SEG 6
SEG 5
SEG 4
SEG 3
SEG 2
SEG 1
SEG 0
EO
D3
D2
D1
D0
XSCL
LP
FR
SEG32
SEG33
SEG34
SEG35
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
V
SSH
V2
V3
V
SS
V
DD
TEST
EI
ECL
SEG31
SEG30
SEG29
SEG28
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PIN DESCRIPTION
Pin Name
SEG0 to SEG63
XSCL
LP
FR
EI
EO
ECL
D0 to D3
TEST
V
DD
, V
SS
V
2
, V
3
, V
SSH
LP falling edge.
Data shift clock input: display data is shifted in on the falling edge of this signal.
Latch pulse for displayed data, falling edge trigger: display data is latched on the
falling edge of this signal.
LCD AC-drive signal
Active high daisy chain enable input
Active high daisy chain enable output
Daisy chain enable clock: the daisy chain enable is propagated on the falling
edge of this clock.
4-bit display data input
Test output
Logic power inputs
LCD drive power inputs
V
SSH
: –14V to –23V
V
DD
≥
V2
≥
V3
≥
V
SSH
Function
Outputs to segment pins of LCD. Output level changes at each latch pulse
427
SED1180
s
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage (1)
Supply voltage (2)
Input voltage
Operating temperature
Storage temperature
Soldering temperature time
Notes:
1. All voltage measurements are based on V
DD
= 0V.
2. V2 and V3 must always satisfy the condition V
DD
≥
V2, V3
≥
V
SSH
.
3. Exceeding the absolute maximum ratings can result in permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
Symbol
V
SS
V
SSH
V
2
, V
3
V
I
T
opr
T
stg
T
sol
Ratings
–7.0 to +0.3
–28.0 to +0.3
V
SS
– 0.3 to +0.3
–20 to +75
–55 to +125
260°C, 10 sec (at lead)
Unit
V
V
V
°C
°C
—
428
SED1180
s
ELECTRICAL CHARACTERISTICS
DC Electrical Characteristics
•
(V
DD
= 0V, V
SS
= –5.0 V
±
10%, T
a
= –20 to 75°C)
Condition
Rating
Min
–5.5
V
SSH
V
SSH
Recommended V
SSH
Operable V
SSH
(see note)
–25.0
–25.0
0.2V
SS
V
SS
–0.3
I
OH
= -0.6 ma
I
OL
= 0.6 ma
0 V
≤
V
I
≤
V
SS
0 V
≤
V
O
≤
V
SS
-0.4
—
—
—
—
—
T
a
= 25°C
—
—
—
—
—
—
Typ
–5.0
—
—
—
—
—
—
—
—
0.05
0.05
—
1/60
5.0
1.9
2.4
3.6
11.5
0.05
Max
–4.5
V
DD
V
DD
–14.0
–5.0
V
DD
–0.3
0.8V
SS
—
V
SS
+0.4
2.0
5.0
6.0
—
8.0
2.9
3.9
7.0
500.0
30
µA
kΩ
Unit
V
V
V
V
V
V
V
V
V
µA
µA
MHz
S
pF
Parameters
Supply voltage (1)
Symbol
V
SS
V
2
V
3
V
SSH
Supply voltage (2)
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Input leakage current
Output leakage current
Shift clock
Frame signal
Input capacitance
Segment output on
resistance
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
XSCL
FR
C
I
R
SEG
V
SSH
= –20.0 V
V
OH
= V
DD
= –0.5 V
V
OL
= V
SSH
= +0.5 V V
SSH
= –14.0 V
SEG bit
V
SSH
= –9.0 V
V
SSH
= –5.0 V
V
SSH
= –25 V, V
SSH
= –5.5 V, V
I
= V
DD
V
SS
= –5.0 V,
V
IH
= V
DD
,
V
IL
= V
SS
,
LP cycle=130
µS,
Quiescent current
I
Q
Operating current for the
logic
I
SSO
FR cycle = 16.7 ms
ECL cycle = 13
µS
XSCL=1.5 MHz,
(duty 50%)
All data input
reversed bit by
bit. All output
pins are open.
V
SS
= –4.5 V,
V
2
= –4.0 V,
V
1
= –16.0 V,
V
SSH
= –20.0 V,
V
IH
= V
DD,
V
IL
= V
SS,
XSCL=1.5 MHz,
(duty 50%),
all data input
reversed bit by
bit. All output
pins are open.
—
90
200
µA
Operating current for the
LCD
I
SSHO
FR cycle = 16.7 ms
ECL cycle = 13
µS
—
40
80
µA
(continued)
429
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