XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
AUGUST 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XRT73LC00A DS3/E3/STS-1 Line Interface Unit
is a low power CMOS version of the XRT73L00A and
consists of a line transmitter and receiver integrated
on a single chip and is designed for DS3, E3 or
SONET STS-1 applications.
XRT73LC00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT73LC00A encodes
input data to either B3ZS (for DS3/STS-1
applications) or HDB3 (for E3 applications) format
and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction the XRT73LC00A performs
equalization on incoming signals, performs Clock
Recovery, decodes data from either B3ZS or HDB3
format, converts the receive data into TTL/CMOS
format, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
The XRT73LC00A also contains a 4-Wire
Microprocessor Serial Interface for accessing the on-
chip Command registers.
FEATURES
•
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00A
•
Meets
E3/DS3/STS-1
Requirements
Jitter
Tolerance
•
Full Loop-Back Capability
•
Transmit and Receive Power Down Modes
•
Full Redundancy Support
•
Contains a 4-Wire Microprocessor Serial Interface
•
Uses Minimum External components
•
Low Power CMOS Design
•
Single +3.3V Power Supply
•
5 V Tolerant pins
•
-40°C to +85°C Operating Temperature Range
•
Available in a 44 pin TQFP package
APPLICATIONS
•
Interfaces to E3, DS3 or SONET STS-1 Networks
•
CSU/DSU Equipment
•
PCM Test Equipment
•
Fiber Optic Terminals
•
Multiplexers
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
TABLE OF CONTENTS
FEATURES ..................................................................................................................................................1
APPLICATIONS ...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT73LC00A .......................................................................................................................... 2
ORDERING INFORMATION...............................................................................................2
F
IGURE
2. P
IN
O
UT OF THE
XRT73LC00A
IN THE
44 P
IN
TQFP ...................................................................................................... 3
PIN DESCRIPTION.............................................................................................................3
ELECTRICAL CHARACTERISTICS ................................................................................11
ABSOLUTE MAXIMUM RATINGS .........................................................................................................11
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................11
AC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................12
F
IGURE
3. T
IMING
D
IAGRAM OF THE
T
RANSMIT
T
ERMINAL
I
NPUT
I
NTERFACE
.................................................................................... 13
F
IGURE
4. T
IMING
D
IAGRAM OF THE
R
ECEIVE
T
ERMINAL
O
UTPUT
I
NTERFACE
.................................................................................. 13
F
IGURE
5. T
RANSMIT
P
ULSE
A
MPLITUDE
T
EST
C
IRCUIT FOR
DS3, E3
AND
STS-1 R
ATES
................................................................ 13
AC ELECTRICAL CHARACTERISTICS (CONT’D) L
INE
S
IDE
P
ARAMETERS
.............................................16
F
IGURE
6. ITU-T G.703 T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
E3 A
PPLICATIONS
..................................................................... 17
F
IGURE
7. B
ELLCORE
GR-499-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
DS3 A
PPLICATIONS
............................................. 17
F
IGURE
8. B
ELLCORE
GR-253-CORE T
RANSMIT
O
UTPUT
P
ULSE
T
EMPLATE FOR
SONET STS-1 A
PPLICATIONS
............................ 18
F
IGURE
9. M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
D
ATA
S
TRUCTURE
.............................................................................................. 18
AC ELECTRICAL CHARACTERISTICS (CONT.) .....................................................................................19
F
IGURE
10. T
IMING
D
IAGRAM FOR THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 19
SYSTEM DESCRIPTION ..................................................................................................20
T
HE
T
RANSMIT
S
ECTION
...............................................................................................................................20
T
HE
R
ECEIVE
S
ECTION
.................................................................................................................................20
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
..................................................................................................20
T
ABLE
1: R
OLE OF
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE PINS WHEN THE
XRT73LC00A
IS OPERATING IN THE
H
ARDWARE
M
ODE
.. 21
1.0 SELECTING THE DATA RATE ............................................................................................................22
T
ABLE
2: S
ELECTING THE
D
ATA
R
ATE FOR THE
XRT73LC00A
VIA THE
E3
AND
STS-1/DS3
INPUT PINS
(H
ARDWARE
M
ODE
) ........... 22
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04) .............................................................................................22
T
ABLE
3: S
ELECTING THE
D
ATA
R
ATE FOR THE
XRT73LC00A V
IA THE
STS-1/DS3
AND THE
E3 B
IT
-
FIELDS
W
ITHIN
C
OMMAND
R
EGISTER
CR4 (HOST M
ODE
)....................................................................................................................................................... 23
2.0 THE TRANSMIT SECTION ..................................................................................................................23
2.1 THE TRANSMIT LOGIC BLOCK .................................................................................................................... 23
F
IGURE
11. T
HE
T
YPICAL
I
NTERFACE FOR THE
T
RANSMISSION OF
D
ATA IN A
D
UAL
-R
AIL
F
ORMAT
F
ROM THE
T
RANSMITTING
T
ERMINAL
E
QUIPMENT TO THE
T
RANSMIT
S
ECTION OF THE
XRT73LC00A ....................................................................................... 24
F
IGURE
12. H
OW THE
XRT73LC00A S
AMPLES THE
D
ATA ON THE
TPDATA
AND
TNDATA I
NPUT
P
INS
.......................................... 24
2.1.1 ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT ............................................................... 24
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................25
F
IGURE
13. T
HE
B
EHAVIOR OF THE
TPDATA
AND
TCLK I
NPUT
S
IGNALS
W
HILE THE
T
RANSMIT
L
OGIC
B
LOCK IS
A
CCEPTING
S
INGLE
-R
AIL
D
ATA
F
ROM THE
T
ERMINAL
E
QUIPMENT
.......................................................................................................................... 25
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .................................................................... 25
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................................ 25
2.3.1 B3ZS ENCODING ....................................................................................................................................................... 25
F
IGURE
14. A
N
E
XAMPLE OF
B3ZS E
NCODING
............................................................................................................................... 26
2.3.2 HDB3 ENCODING ....................................................................................................................................................... 26
F
IGURE
15. A
N
E
XAMPLE OF
HDB3 E
NCODING
.............................................................................................................................. 26
2.3.3 ENABLING/DISABLING THE HDB3/B3ZS ENCODER ............................................................................................. 26
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02) .............................................................................................27
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ............................................................................................ 27
2.4.1
C
OMMAND
2.4.2
C
OMMAND
2.4.3
2.4.4
ENABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ......................................................................................... 27
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................27
DISABLING THE TRANSMIT LINE BUILD-OUT CIRCUIT ........................................................................................ 28
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) .............................................................................................28
DESIGN GUIDELINE FOR SETTING THE TRANSMIT LINE BUILD-OUT CIRCUIT ................................................ 28
THE TRANSMIT LINE BUILD-OUT CIRCUIT AND E3 APPLICATIONS................................................................... 28
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT73LC00A TO THE LINE ...................................... 28
F
IGURE
16. R
ECOMMENDED
S
CHEMATIC FOR
I
NTERFACING THE
T
RANSMIT
S
ECTION OF THE
XRT73LC00A
TO THE
L
INE
................. 29
T
RANSFORMER
R
ECOMMENDATIONS
................................................................................................... 29
3.0 THE RECEIVE SECTION .....................................................................................................................31
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