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XC2S150-5FGG256I

Description
Field Programmable Gate Array, 864 CLBs, 150000 Gates, 263MHz, 3888-Cell, PBGA256, FBGA-256
CategoryProgrammable logic devices    Programmable logic   
File Size76KB,6 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance  
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XC2S150-5FGG256I Overview

Field Programmable Gate Array, 864 CLBs, 150000 Gates, 263MHz, 3888-Cell, PBGA256, FBGA-256

XC2S150-5FGG256I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid2025410791
Parts packaging codeBGA
package instructionBGA, BGA256,16X16,40
Contacts256
Reach Compliance Codecompliant
Country Of OriginTaiwan
ECCN codeEAR99
Factory Lead Time52 weeks
Samacsys ManufacturerXILINX
Samacsys Modified On2021-11-24 08:49:58
YTEOL3
maximum clock frequency263 MHz
Combined latency of CLB-Max0.7 ns
JESD-30 codeS-PBGA-B256
JESD-609 codee1
length17 mm
Humidity sensitivity level3
Configurable number of logic blocks864
Equivalent number of gates150000
Number of entries260
Number of logical units3888
Output times260
Number of terminals256
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize864 CLBS, 150000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)260
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height2 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
0
R
Spartan-IIE 1.8V FPGA
Automotive XA Product Family:
Introduction and Ordering
0
DS106-1 (v2.0) August 9, 2013
0
Product Specification
Guaranteed to meet full electrical specifications over
T
J
= –40°C to +125°C
Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Very low cost
System-level features
- SelectRAM+™ hierarchical memory:
·
16 bits/LUT distributed RAM
·
Configurable 4K-bit true dual-port block RAM
·
Fast interfaces to external RAM
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
·
Eliminate clock distribution delay
·
Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Low-cost packages available in all densities
- 19 high-performance interface standards
·
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
·
LVDS and LVPECL differential I/O
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
Fully supported by powerful Xilinx ISE development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions
Introduction
The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-
grammable Gate Array family is specifically designed to
meet the needs of high-volume, cost-sensitive automotive
electronic applications. The family gives users high perfor-
mance, abundant logic resources, and a rich feature set, all
at an exceptionally low price. The five-member family offers
densities ranging from 50,000 to 300,000 system gates, as
shown in
Table 1.
System performance is supported beyond
200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
XA devices are available in both the extended-temperature
Q-grade (-40
°
C to +125
°
C) and industrial I-grade (-40
°
C to
+100
°
C) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of conven-
tional ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement neces-
sary (impossible with ASICs).
Features
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade
Table 1:
XA Spartan-IIE FPGA Family Members
Logic
Cells
1,728
2,700
3,888
5,292
6,912
Typical
System Gate Range
(Logic and RAM)
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
CLB
Array
(R x C)
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
Total
CLBs
384
600
864
1,176
1,536
Maximum
Available
User I/O
(1)
102
102
182
182
182
Maximum
Differential
I/O Pairs
83
86
114
120
120
Distributed
RAM Bits
24,576
38,400
55,296
75,264
98,304
Block
RAM Bits
32K
40K
48K
56K
64K
Device
XA2S50E
XA2S100E
XA2S150E
XA2S200E
XA2S300E
Notes:
1. User I/O counts include the four global clock/user input pins. See details in
Table 3, page 5
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS106-1 (v2.0) August 9, 2013
Product Specification
www.xilinx.com
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